Flash Memory Control Driver Architecture for Area Reduction
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Solution Overview
Problem
Existing row decoders for flash memory are complex and consume excessive chip area due to their architecture, which leads to increased program disturb and inefficiencies in layout.
Innovation Solution
A simplified control driver architecture utilizing a single level shift circuit, pull-up, and pull-down transistors, along with a select circuit, to generate control line signals efficiently, reducing chip area and program disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional row decoder architecture with multiple level shift circuits and pull-up/pull-down transistors is used, then the control driver can drive memory units effectively, but the chip area increases and program disturb occurs
Solution Approach 1:
The patent merges multiple level shift circuits into a single level shift circuit that serves multiple control drivers. This consolidation reduces the total number of transistors and circuit components, thereby reducing chip area while maintaining the ability to drive memory units effectively and minimize program disturb.
Solution Approach 2:
The single level shift circuit is designed to provide level shifting functionality for multiple control drivers simultaneously. This multi-functional approach allows one circuit to replace what would traditionally require multiple separate circuits, reducing overall chip area while maintaining reliable operation.
2Area of stationary object
If a simplified control driver architecture is used, then chip area is reduced, but the ability to generate control line signals effectively may be compromised
Solution Approach 1:
The patent combines multiple control driver functions into a simplified architecture with shared level shift and pull-up/pull-down transistor resources. This merging reduces chip area while the design ensures that control line signals are still generated effectively through proper timing and control logic.
Solution Approach 2:
The simplified architecture uses dynamic control mechanisms where a single level shift circuit and shared transistors are controlled by select signals to provide the necessary control line signals at different times. This dynamic operation maintains signal generation effectiveness while reducing static circuit complexity and area.
Data Source
AI summary
A control driver for non-volatile memory includes a driving circuit, a level shift up circuit, and a select circuit. The select circuit receives a plurality of decoding signals, asserts a select signal when all of the decoding signals are asserted, and does not assert the select signal when any of the decoding signals is not asserted. The level shift up circuit receives the select signal, outputs the pull-up signal at a first voltage when the select signal is asserted, and outputs the pull-up signal at a second voltage when the select signal is not asserted. The driving circuit has a pull-up transistor for pulling up a control line signal according to the pull-up signal, and a pull-down transistor for pulling down the control line signal according to the pull-up signal.