Flash Memory Cell with Control Gate Facing Channel
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Solution Overview
Problem
Conventional flash memory technologies face challenges in downsizing due to degradation of the gate insulating film, high voltage requirements, and high probability of write errors, which hinder scaling and reliability.
Innovation Solution
A nonvolatile semiconductor storage unit with a control transistor and a floating gate structure where the control gate electrode directly faces the channel, allowing for a thinner gate insulating film and lower voltage operation, and using a high-K insulating film to reduce channel impurity concentration and minimize gate disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gate insulating film is thinned to enable downsizing, then the memory cell size is reduced, but the insulating film degrades due to write/erase cycles
Solution Approach 1:
The patent changes the material parameter of the gate insulating film from conventional silicon oxide to high-K insulating film, which has higher dielectric constant. This allows the film to be thinner while maintaining sufficient insulation performance and durability against write/erase cycles, thus enabling downsizing without sacrificing reliability
Solution Approach 2:
The patent employs a composite gate insulating film structure comprising multiple layers including high-K insulating film, silicon oxide film, and silicon nitride film. This composite structure combines the advantages of different materials to achieve both thinness for downsizing and durability for reliable operation
2Volume of moving object
If the channel length is decreased for downsizing, then the memory cell density is increased, but higher gate voltage is required to prevent punch-through
Solution Approach 1:
The patent introduces a lightly-doped drain region (LDD) structure that changes the impurity concentration parameter in the drain region. This creates a gradual doping profile that reduces the electric field concentration at the drain junction, preventing punch-through effect even with short channel length, thus enabling downsizing without increasing gate voltage
3Ease of manufacture
If high voltage is applied to the control gate electrode for write operation, then electron injection into the floating gate is achieved, but write errors occur due to gate disturbance in unselected cells
Solution Approach 1:
The patent applies local quality by creating different impurity concentration regions: the LDD region with low impurity concentration near the floating gate to reduce electric field and prevent disturbance, while maintaining higher impurity concentration in other regions for proper transistor operation. This localized doping strategy enables write operation while minimizing gate disturbance in unselected cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables high-density, high-speed, and high-reliability memory cells by eliminating the need for thick gate insulating films and reducing voltage requirements, while minimizing write errors.
Implementation Method 1
A voltage of 12 V is applied to the source to apply a high electric field to the gate insulating film 203 so that electrons accumulated in the floating gate 204 are removed to the source by the FN (Fowler-Nordheim) current
Implementation Method 2
A voltage of 12 V is applied to the control gate electrode 206 to generate CHE (Channel Hot Electrons) in the channel, and some of them are injected into the floating gate
Data Source
AI summary
A diffusion layer (102) is formed in the surface region of a semiconductor substrate (101). A control gate electrode (103) is formed on the substrate. An interlayer dielectric film (108) covers the entire surface of the substrate. A drain leader line (104) made of a semiconductor such as n-type polysilicon is led from the drain region, and a source leader line (107) is led from the source region through the interlayer dielectric film. The drain leader line is surrounded by an annular floating gate (105). In erase, for example, the control gate is set to a ground potential, and a positive voltage is applied to the drain leader line to remove electrons in the floating gate to the drain leader line. In write, positive voltages are applied to the control gate electrode and drain leader line to generate CHE and inject hot electrons into the floating gate. This allows to thin the gate insulating film of a flash memory, increase the degree of integration of a nonvolatile memory, and lower the driving voltage.