Flash Memory Control Gate Contact Formation via Etch Stop Layers
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing costs and increasing efficiency in manufacturing semiconductor memory devices, particularly in lithography operations, as new generations of integrated circuits demand higher performance and greater functionality.
Innovation Solution
The method involves a manufacturing process for flash memory cells that eliminates certain etching operations, such as those associated with forming control gate contacts, and uses specific layer formations like first and second etch stop layers, spacer layers, and interlayer dielectric materials to enhance efficiency and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography operations are performed to form control gate contacts, then manufacturing precision is improved, but productivity is reduced and costs increase
Solution Approach 1:
The patent extracts and eliminates the photolithography and ashing operations from the conventional manufacturing process. Instead of forming control gate contacts through multiple lithography steps, the invention uses a direct etching approach through the interlayer dielectric layer, removing unnecessary process steps while maintaining contact formation precision
Solution Approach 2:
The patent skips the intermediate ashing step that is typically required after photolithography. The process transitions directly from patterning to etching through the interlayer dielectric, rushing through the manufacturing sequence to improve productivity without sacrificing the precision needed for control gate contact formation
2Manufacturing precision
If multiple lithography operations are performed, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The patent merges multiple separate lithography operations into a single patterning step. The first and second etch stop layers are formed and patterned together in one lithography process, eliminating the need for separate alignment and patterning operations while maintaining the required layer alignment precision
Solution Approach 2:
The single lithography operation performs multiple functions simultaneously: it defines the pattern for the first etch stop layer, the second etch stop layer, and the control gate contact alignment all in one process step, reducing total manufacturing time while maintaining precision through a unified patterning approach
3Device complexity
If conventional manufacturing processes with multiple steps are used, then device complexity is reduced, but productivity is reduced
Solution Approach 1:
The patent performs preliminary actions by forming the first and second etch stop layers with integrated patterning before the main etching operations. This preliminary structuring is done in a way that anticipates subsequent steps, allowing direct etching to control gate contacts without requiring intermediate ashing or re-patterning operations
Solution Approach 2:
The patent establishes continuity of useful action by eliminating idle steps such as ashing between lithography and etching operations. The manufacturing process flows continuously from patterning through etching of the interlayer dielectric to control gate contact formation, maintaining productive action throughout without interruptions that would reduce manufacturing efficiency
Data Source
AI summary
A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.