Flash Memory Control Gate Recess for Leakage Reduction
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Solution Overview
Problem
Flash memory devices formed using existing technology have low stability and poor reliability due to increased resistivity of the control gate layer and insufficient space between memory cells, leading to leakage currents and reduced performance.
Innovation Solution
A method involving the formation of a metal silicide layer in the control gate layer using a self-aligned silicide process, with a second mask layer to recess the control gate layer and form an electrical contact layer, and a barrier layer to isolate the conductive structure, reducing the size of the exposed control gate layer and preventing direct contact with the conductive structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a self-aligned electrical contact process is used to reduce the size of the flash memory cell, then the area of the memory cell is reduced, but the stability and reliability of the device deteriorates due to increased resistivity and leakage currents
Solution Approach 1:
The control gate layer is divided into two distinct parts: a first control gate layer portion that remains in contact with the substrate for electrical connection, and a second control gate layer portion that is removed to create the electrical contact opening. This segmentation allows the memory cell to maintain small area while ensuring proper electrical isolation and connection, thereby improving reliability without sacrificing miniaturization benefits
Solution Approach 2:
The method performs preliminary removal of the second control gate layer portion before forming the electrical contact opening. This preliminary action ensures that the control gate layer does not interfere with subsequent electrical contact formation, preventing leakage currents and ensuring proper isolation between the conductive structure and control gate, thus improving device stability
2Reliability
If the control gate layer is kept intact to maintain electrical connection, then the electrical conductivity is maintained, but the space between memory cells is insufficient leading to leakage currents
Solution Approach 1:
The method extracts or removes the second control gate layer portion from over the substrate in the region where the electrical contact opening will be formed. This extraction creates the necessary space for the electrical contact opening without requiring additional mask layers or complex process steps, thereby achieving proper electrical isolation while maintaining process simplicity
Solution Approach 2:
The control gate layer itself serves dual purposes: it provides the control function when intact, and it automatically creates the opening structure when the second portion is removed. The removed portion defines the boundaries of the electrical contact opening, eliminating the need for separate definition steps and reducing overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the stability and reliability of flash memory devices by reducing resistivity, preventing leakage currents, and improving performance by ensuring desired electrical isolation between the conductive structure and the control gate layer.
Implementation Method 1
enhances the stability and reliability of flash memory devices by reducing resistivity
Implementation Method 2
preventing leakage currents, and improving performance by ensuring desired electrical isolation between the conductive structure and the control gate layer
Data Source
AI summary
Various embodiments provide memory devices and methods for forming the same. A substrate is provided, the substrate having one or more adjacent memory cells formed thereon. Each memory cell includes a gate structure, a control gate layer, and a first mask layer. A portion of the control gate layer is removed, to reduce a size of an exposed portion of the control gate layer in a direction parallel to a surface of the substrate. An electrical contact layer is formed on an exposed sidewall of the control gate layer and an exposed surface of the substrate. A barrier layer is formed on a sidewall of the memory cell. A conductive structure is formed on the substrate. The conductive structure has a significantly larger distance from control gate layer than from the gate structure, and the barrier layer forms an isolation layer between the conductive structure and the control gate layer.