Flash Memory Control Right Distribution for Write Latency

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Solution Overview

Problem

Flash memory devices face challenges in completing write commands within a predetermined time due to the need to erase entire physical blocks, which affects data management and efficiency, especially when multiple write operations are required.

Innovation Solution

Implementing a multi-threaded approach within the flash memory storage device, where a first thread and a second thread manage distinct program units, allowing for the distribution of control rights to ensure efficient execution of write commands, even if the first thread has not completed its operation, by prioritizing the second thread to meet time constraints specified by SD card standards.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the first thread completes its program operation before the second thread can access the flash memory chip, then the first thread ensures data integrity, but the write command completion time exceeds the predetermined time limit

Engineering Contradiction:

Improvedata integrityVSAvoidwrite command completion time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The flash memory chip is divided into multiple physical blocks that can be independently accessed. The program management method segments the write operations so that different threads can work on different physical blocks simultaneously, allowing the second thread to access available blocks while the first thread completes its operations on other blocks.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The control right distribution mechanism dynamically allocates access permissions to different threads based on the current state of physical blocks. When the first thread releases control after completing its program operation, the second thread can immediately acquire control and access the flash memory chip if time constraints require it.

Inventive Principle:

Principle #15Dynamics

2Stability of the object's composition

If the entire physical block is erased to reprogram a physical page, then the flash memory structure is maintained, but the data management efficiency decreases

Engineering Contradiction:

Improveflash memory structureVSAvoiddata management efficiency

Core Design Contradiction:

Stability of the object's compositionVSProductivity

Solution Approach 1:

The flash memory is segmented into multiple physical blocks, and the system can selectively erase and program individual blocks rather than requiring entire blocks to be erased for every reprogram operation. This segmentation allows more flexible and efficient data management.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the operational parameters by allowing different threads to access different physical blocks with different erasure states. The system tracks which blocks are erased and which contain valid data, allowing efficient reuse of erased blocks without requiring complete block erasure for every write operation.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If multiple write operations are executed sequentially by a single thread, then data consistency is maintained, but the completion time for all write commands exceeds the predetermined time limit

Engineering Contradiction:

Improvedata consistencyVSAvoidwrite command throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

Multiple write operations are segmented and distributed across different threads, with each thread responsible for specific physical blocks. This allows parallel execution of write operations while maintaining data consistency through proper control right management and block allocation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges multiple write operations into parallel execution by allocating different physical blocks to different threads. The control circuit manages the merging of results and ensures that all write commands are completed within the predetermined time limit through coordinated thread execution.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9507702B2Method of performing write access by distributing control rights to threads, memory controller and flash memory storage device using the same

Publication Date: 2016.11.29 SAMSUNG ELECTRONICS CO LTD

AI summary

A flash memory storage device, a controller thereof, and a programming management method thereof are provide for the flash memory storage device including a flash memory chip, wherein at least a first thread and a second thread are to be implemented within the flash memory storage device. The method includes defining a predetermined programming unit and receiving a first write command sent by a host. The method also includes distributing a control right of the flash memory chip to the first thread if the first write command is determined to be executed by the first thread, and controlling the first thread to release the control right of the flash memory chip after the first thread finishes a programming operation of the predetermined programming unit.