Flash Memory Control Unit Host Memory Buffer Mapping
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in achieving high data reliability and efficiency while maintaining low manufacturing costs, particularly in managing mapping relationships between logical and physical addresses in flash memory systems.
Innovation Solution
A control unit with a host memory buffer (HMB) is employed to dynamically manage physical-to-logical and logical-to-physical mapping tables, utilizing buffers to update and reverse mapping information efficiently, reducing the need for large capacity memory and extending the life of flash memory by minimizing direct accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If mapping information is stored entirely in the non-volatile memory device, then data reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The mapping table is segmented into two parts: a first mapping table stored in the non-volatile memory device and a second mapping table stored in the host memory buffer. This segmentation allows the device to maintain essential mapping information locally while offloading redundant or less frequently accessed mapping data to the host, thereby reducing device complexity and manufacturing cost while preserving data reliability through distributed storage.
Solution Approach 2:
The host memory buffer acts as an intermediary between the host and the non-volatile memory device, temporarily storing mapping information. This intermediary approach reduces the burden on the non-volatile memory device by handling mapping table storage and updates in the host's memory space, simplifying device architecture while maintaining reliable mapping functionality through coordinated access between host and device.
2Manufacturing precision
If mapping tables are updated frequently, then data accuracy is improved, but flash memory lifespan decreases due to increased write cycles
Solution Approach 1:
Mapping table updates are performed preliminarily in the host memory buffer before being committed to the non-volatile memory device. This preliminary action allows the host to prepare and validate mapping updates in its own memory space, ensuring data accuracy through host-side validation while deferring actual writes to the flash memory until necessary, thereby reducing write cycle frequency and extending flash memory lifespan.
Solution Approach 2:
The host memory buffer serves as an intermediary that absorbs frequent mapping update operations. By storing and managing mapping table updates in the host's volatile memory, the system achieves high data accuracy through frequent updates without subjecting the flash memory to excessive write cycles, thus preserving flash memory lifespan while maintaining mapping data accuracy.
3Quantity of substance
If large capacity memory is used for mapping tables, then mapping completeness is improved, but manufacturing cost increases
Solution Approach 1:
The host memory buffer, which serves multiple functions including general-purpose data buffering and processing, is utilized to store mapping table information. This multi-functional use of the host's existing memory resources provides the necessary mapping table capacity without requiring additional dedicated memory components in the non-volatile memory device, thereby maintaining complete mapping functionality while reducing manufacturing cost.
Solution Approach 2:
The host system utilizes its own memory resources (host memory buffer) to store and manage mapping table information, rather than requiring the non-volatile memory device to provide dedicated large-capacity memory for this purpose. This self-service approach allows the mapping table capacity to be provided by the host's existing memory infrastructure, eliminating the need for additional memory components in the device and thereby reducing manufacturing cost while maintaining complete mapping capabilities.
Data Source
AI summary
A control unit for a data storage system is shown, which provides at least two buffers for updating mapping information through a host memory buffer HMB. A first buffer is provided for dynamic management of a physical-to-logical mapping table F2H that records a mapping relationship which maps a physical address within a target block to a logical address of a sector of user data stored at the physical address. The control unit performs reverse conversion on the mapping relationship to get reversed mapping information for the logical address and, accordingly, selects a target logical-to-physical mapping sub-table. A second buffer is provided to buffer the target logical-to-physical mapping sub-table when the target logical-to-physical mapping sub-table is read from the host memory buffer HMB. The control unit updates the target logical-to-physical mapping sub-table on the second buffer based on the reversed mapping information about the logical address.