Flash Memory Controller Adaptive Decoding for QLC Bit Error Reduction

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Solution Overview

Problem

Existing flash memory devices, particularly those with quadruple level cell (QLC) flash memories, face challenges with increased bit error rates and inefficient reading mechanisms, as traditional sensing schemes are not effective for high-level memory cells.

Innovation Solution

A method for accessing flash memory modules that involves reading cumulative distribution information from memory cells to determine a target decoding flow, which can be either a first or second decoding flow, and using this flow to decode readout information from additional memory cells, thereby enhancing performance without introducing side effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional sensing schemes are used for reading data from QLC flash memories, then the reading mechanism is simple, but the bit error rate increases and decoding effectiveness deteriorates

Engineering Contradiction:
Improvebit error rateVSAvoiddecoding mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by reading a first word line to obtain cumulative distribution information before reading the second word line. This preliminary reading step allows the system to determine the appropriate decoding flow in advance, improving decoding effectiveness for QLC flash memories without increasing the bit error rate during actual data retrieval

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamics by making the decoding flow selectable and adaptive. The system dynamically chooses between a first decoding flow and a second decoding flow based on the cumulative distribution information obtained from preliminary reading. This dynamic adaptation allows the decoding mechanism to optimize its approach for different data conditions, improving reliability without requiring a completely static complex decoding structure

Inventive Principle:
Principle #15Dynamics

2Reliability

If multiple decoding flows are implemented to improve decoding effectiveness, then the reliability improves, but the device complexity increases

Engineering Contradiction:
Improvedecoding effectivenessVSAvoiddecoding flow structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by using cumulative distribution information as a decision parameter to select between different decoding flows. The cumulative distribution characteristics of the flash memory data determine which decoding approach is used, allowing the system to adapt to different data states without hardcoding multiple complex decoding paths. This parameter-based selection simplifies the overall structure while maintaining multiple decoding capabilities

Inventive Principle:
Principle #35Parameter changes

3Reliability

If cumulative distribution information is read from memory cells to determine decoding flow, then the decoding effectiveness improves, but the access time increases

Engineering Contradiction:
Improvedecoding effectivenessVSAvoidmemory access time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by reading only a first word line to obtain cumulative distribution information, rather than reading all word lines before decoding. This partial reading approach provides sufficient information to determine the appropriate decoding flow without incurring the full time cost of reading the entire data set, thus balancing decoding effectiveness with access time efficiency

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11210028B2Method for accessing flash memory module and associated flash memory controller and electronic device
Publication Date: 2021.12.28 SILICON MOTION INC
  • US11210028B2 patent drawing
  • US11210028B2 patent drawing
  • US11210028B2 patent drawing

AI summary

The present invention discloses a method for accessing a flash memory module, wherein the flash memory module comprises a plurality of block, each block is implemented by a plurality of word lines, and each word line comprises a plurality of memory cells supporting a plurality of states. The method comprises the steps of: reading the memory cells of at least a first word line of a specific block of the plurality of blocks to obtain a cumulative distribution information of the states of the memory cells; determining a target decoding flow selected from at least a first decoding flow and a second decoding flow according to the cumulative distribution information; reading the memory cells of a second word line to obtain readout information of the second word line; and using the target decoding flow to decode the readout information of the second word line.