Flash Memory Controller Fast Slow Address Segmentation
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Solution Overview
Problem
MLC NAND flash memories have lower access speed compared to SLC NAND flash memories, which affects the efficiency of flash memory storage devices, and there is a need to improve this to enhance storage device performance.
Innovation Solution
A data storage method that utilizes a flash memory controller to differentiate between fast and slow physical addresses based on usage rates, employing a fast mode that only uses fast physical addresses for data storage when the usage rate is below a threshold, thereby optimizing data writing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC NAND flash memory is used to increase storage capacity and reduce cost, then storage capacity increases and cost decreases, but access speed deteriorates
Solution Approach 1:
The patent segments the physical addresses into fast physical addresses and slow physical addresses based on usage rates. The memory controller monitors usage rates and selectively maps logical addresses to different types of physical addresses, thereby segmenting the storage space to optimize both speed and capacity utilization
Solution Approach 2:
The patent implements dynamic address mapping where the memory controller dynamically adjusts the mapping between logical addresses and physical addresses based on real-time usage rate monitoring. When usage rates are low, fast physical addresses are prioritized; when usage rates increase, the system adapts by incorporating slow physical addresses, creating a dynamic optimization mechanism
2Quantity of substance
If all physical addresses are used for data storage to maximize capacity utilization, then storage capacity utilization increases, but data writing speed deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the quality of different physical addresses based on their usage rates. Fast physical addresses with lower usage rates are prioritized for data storage to maintain high writing speeds, while slow physical addresses with higher usage rates are used when necessary, creating localized optimization within the storage system
Data Source
AI summary
A data storage method for storing data into a flash memory chip is provided. The flash memory chip has a plurality of physical addresses, and these physical addresses include a plurality of fast physical addresses and a plurality of slow physical addresses. In the data storage method, the usage rate of the physical addresses is monitored. When the usage rate is not larger than a usage rate threshold value, only the fast physical addresses are used for storing the data into the flash memory chip. When the usage rate is larger than the usage rate threshold value, the fast physical addresses and the slow physical addresses are used for storing the data into the flash memory chip. Thereby, the speed of storing data into the flash memory chip is effectively increased.