Flash Memory Controller Address Verification via Checking Code
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Solution Overview
Problem
Conventional flash memory storage systems cannot ensure data correctness due to signal noise during command transmission, leading to incorrect data access and reliability issues, particularly in solid-state drives that require high data reliability.
Innovation Solution
A data accessing method and controller that uses a checking code, such as a CRC, to verify the correctness of the physical address accessed in flash memory by generating and storing a checking code along with data, allowing for error correction and re-reading if the address is incorrect, ensuring data is read from the correct physical address.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC is used to correct data errors, then data correctness is improved, but the system cannot ensure the read address is correct due to signal noise during command transmission
Solution Approach 1:
The patent applies preliminary action by writing a checking code along with the data into the physical address before reading. This checking code is generated in advance based on the logical address and physical address mapping, allowing the system to verify address correctness before data transmission occurs. This resolves the contradiction by ensuring both data correctness and address accuracy through proactive verification rather than reactive correction.
Solution Approach 2:
The patent implements feedback by reading the checking code from the physical address and comparing it with the expected checking code derived from the logical address. This feedback mechanism allows the system to detect whether the read operation accessed the correct physical address, and if not, to request re-reading from the correct address. This feedback loop resolves the contradiction by enabling both address accuracy verification and data correctness assurance.
2Ease of operation
If a mapping table is used to translate logical addresses to physical addresses, then data access functionality is improved, but signal noise may cause incorrect address translation and data access errors
Solution Approach 1:
The patent introduces an intermediary mechanism by adding a checking code field to the data structure stored in physical addresses. This checking code acts as a mediator between the logical address mapping table and the actual data storage, providing an additional verification layer that confirms the physical address accessed corresponds to the intended logical address. This intermediary verification resolves the contradiction by maintaining ease of operation through the mapping table while ensuring reliability through the checking code verification.
3Speed
If conventional read commands are transmitted without verification, then transmission speed is maintained, but incorrect data may be transmitted to the host due to address misjudgement
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing the checking code in the physical address before the read operation occurs. This allows the verification to happen during the read process itself without requiring separate verification steps that would slow down transmission. The checking code is ready in advance, enabling fast verification while maintaining transmission speed, thus resolving the contradiction between speed and reliability.
Data Source
AI summary
Data accessing method for a flash memory, and a controller and a storage system using the same are provided. The data accessing method includes reading data from a physical address of a flash memory according to a physical address to be read corresponding to a logical address to be read in a read command, and determining whether or not the read physical address is the physical address to be read. The data accessing method also includes transmitting the data only if the read physical address is the physical address to be read. Accordingly, it is possible to ensure the transmitted data is data to be accessed by the read command.