Flash Memory Controller Addressing Beyond 32-Bit Limit
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Solution Overview
Problem
Current flash memory communication schemes are limited to a 32-bit length logical address space, restricting the maximum capacity of flash memory to 2 TB and failing to support addressing capabilities beyond this limit.
Innovation Solution
A novel communication scheme is introduced that allows a flash memory controller in an SD memory card to report capacities greater than 2 TB to a host device by using a combination of partial address parameters to form a complete address parameter, enabling support for addressing beyond the 32-bit length logical address space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a 32-bit length logical address space is used for communication between host device and flash memory, then the communication scheme is simple and compatible with existing standards, but the maximum capacity of flash memory is limited to 2 TB
Solution Approach 1:
The patent segments the address parameter into multiple parts (first partial address parameter and second partial address parameter) that are transmitted separately through different command interfaces. This allows the system to overcome the 32-bit address limitation without requiring a completely new communication protocol, thereby extending addressing capability while maintaining compatibility with existing standards.
Solution Approach 2:
The patent makes existing command interfaces (CMD22, CMD31, CMD39, CMD41, CMD51) serve dual purposes: they continue to function as before for standard operations while also being used to transmit partial address parameters for extended addressing. This multi-functionality allows the system to support both traditional 2 TB and new larger capacity flash memories using the same communication infrastructure.
2Quantity of substance
If the maximum capacity of flash memory is limited to 2 TB to maintain compatibility with existing communication schemes, then the communication scheme remains simple and widely compatible, but the capacity is insufficient for future applications requiring larger storage
Solution Approach 1:
The patent adds a new dimension to the address parameter transmission by using multiple command interfaces sequentially. Instead of relying on a single 32-bit address field, the system transmits address information across multiple dimensions (different commands, different timing sequences), enabling capacities beyond 2 TB while maintaining compatibility with existing single-command interfaces.
Solution Approach 2:
The patent performs preliminary actions by having the host device send the first partial address parameter through one command interface before sending the second partial address parameter through another command interface. This sequential preliminary transmission of address components allows the flash memory controller to reconstruct the complete address and support larger capacities while maintaining backward compatibility.
Data Source
AI summary
A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.