Flash Memory Controller Data Dispersion Management

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Solution Overview

Problem

Flash memory writing speed is hindered by the need to erase entire physical blocks, leading to inefficiencies in processing valid and invalid data, especially when data is not written in the order of logical addresses.

Innovation Solution

A data writing method that configures logical page addresses into logical blocks, records data dispersion degrees, and writes data into flash memory based on these degrees and physical page addresses, ensuring the data dispersion degree of each logical block does not exceed a threshold, thereby optimizing data placement and reducing write time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the entire physical block is erased before writing data, then data can be written into flash memory, but writing speed decreases due to the time-consuming erasure process

Engineering Contradiction:
Improvewriting speedVSAvoidtime for erasure process
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-erasing physical blocks and maintaining a pool of pre-erased physical blocks before actual data writing occurs. The controller proactively erases physical blocks in advance and stores them in a buffer, so when host write commands arrive, pre-erased blocks are immediately available for writing without waiting for erasure operations. This resolves the contradiction by performing the time-consuming erasure operation beforehand, making the actual writing process faster.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If data is written based on host's logical address order, then data management is simple, but data dispersion increases when hosts write in random order

Engineering Contradiction:
Improvedata management simplicityVSAvoidwrite command execution speed
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent introduces an intermediary layer (the controller with logical block configuration) between the host and the physical flash memory structure. The controller translates host logical addresses into physical block addresses, allowing the host to write data in any order while the controller reorganizes and consolidates data into physical blocks. This intermediary resolves the contradiction by absorbing the complexity of address translation and data consolidation, enabling both simple host operation and efficient physical data management.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If physical blocks are frequently erased and rewritten, then data storage flexibility is maintained, but the number of valid data pages scattered across physical blocks increases

Engineering Contradiction:
Improvedata storage flexibilityVSAvoiddata distribution complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the flash memory into distinct logical blocks that are further divided into physical blocks, with each logical block independently managing its data. This segmentation allows data from a single logical block to be consolidated into fewer physical blocks, reducing the scattering effect. When a logical block needs to be erased or rewritten, only its associated physical blocks are affected, not the entire flash memory. This resolves the contradiction by isolating data management to smaller units, maintaining flexibility while reducing overall data distribution complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8250292B2Data writing method for a flash memory, and controller and storage system using the same
Publication Date: 2012.08.21 PHISON ELECTRONICS
  • US8250292B2 patent drawing
  • US8250292B2 patent drawing
  • US8250292B2 patent drawing

AI summary

A data writing method for writing data from a host system into a flash memory chip is provided. The method includes configuring a plurality of logical page addresses, grouping the logical page addresses into a plurality of logical blocks, and recording the data dispersion degree of each of the logical blocks. The method also includes receiving write-in data from the host system, identifying a logical block that a logical page address to be written by the host system belongs to, and writing the write-in data into the flash memory chip according to the data dispersion degree of the logical block, wherein the data dispersion degree of each of the logical blocks is not larger than a logical block data dispersion degree threshold value. Accordingly, the method can effectively reduce the time for executing a host write command.