Flash Memory Controller Data Maintenance for Error Control
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Solution Overview
Problem
Flash memory systems, such as NAND Flash, face limitations in error correction during data storage, leading to reduced memory space due to marking pages or blocks as 'bad' when error correction fails, which is inefficient in managing bit errors and identifying damaged units.
Innovation Solution
A data maintenance method involving a controller that performs multiple read processes on single-level-cell units to program data into triple-level cell units, checks for successful read operations, and uses error correction to determine if any single-level-cell units have failed, allowing for the identification and management of damaged units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encoding and decoding procedures are used to correct bit errors in flash memory, then error correction capability is improved, but memory space is reduced due to marking pages or blocks as bad when errors exceed correction limits
Solution Approach 1:
The patent performs preliminary read verification on single-level-cell units before programming data into triple-level cell units. By checking read success in advance and identifying damaged units beforehand, the system prevents wasting TLC units on bad SLC data, thereby reducing the need to mark TLC units as bad and preserving memory space while maintaining reliability
Solution Approach 2:
The patent introduces single-level-cell units as an intermediary storage layer between data sources and triple-level cell units. The SLC units serve as a verification buffer, allowing the system to check data integrity before final storage in TLC units, thus reducing error propagation and minimizing bad block marking in the main storage area
2Measurement precision
If multiple read processes are performed on single-level-cell units before programming into triple-level cell units, then identification of damaged units is improved, but processing time increases
Solution Approach 1:
The patent performs a predetermined number of read processes on SLC units, which may be fewer than exhaustive testing would require, but sufficient to identify clearly damaged units. This partial action approach achieves adequate identification accuracy while limiting the time penalty, balancing verification thoroughness with processing efficiency
Solution Approach 2:
The read verification processes are performed preliminarily on SLC units before data is committed to TLC units. By doing the verification work upfront on the intermediary SLC layer, the system identifies damaged units early in the process flow, preventing wasted programming operations and reducing overall processing time despite the additional verification steps
Data Source
AI summary
The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of single-level-cell units and a plurality of triple-level cell units. The controller performs a first predetermined number of read processes on a second predetermined number of specific single-level-cell units to program data stored in the second predetermined number of specific single-level-cell units into a specific triple-level cell unit of the triple-level cell units and determines whether any of the second predetermined number of specific single-level-cell units has not been read successfully by any of the read processes when the specific triple-level cell unit cannot be read successfully.