Flash Memory Controller Driving Current Adjustment
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Solution Overview
Problem
Flash memory controllers with constant driving current levels fail to maintain data-access operations when controlling more than four flash memories, leading to errors due to insufficient power and increased noise in data signals.
Innovation Solution
A flash memory controller with a processor and driving current generator that calculates and adjusts the driving current level based on the total number of flash memories, ensuring each memory receives a sufficient current to prevent errors and signal degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a flash memory controller provides a driving current with a constant level to control multiple flash memories, then the device complexity is reduced and ease of operation is improved, but the reliability of data-access operations deteriorates when the number of flash memories exceeds four due to insufficient current per memory
Solution Approach 1:
The patent implements dynamic adjustment of the driving current level based on the detected number of flash memories. The controller transitions from a static constant current approach to a dynamic current regulation system that adapts to the actual number of connected memories, ensuring each memory receives sufficient current while maintaining ease of operation through automated detection and adjustment
Solution Approach 2:
The patent changes the driving current parameter from a fixed constant level to a variable level that is adjusted according to the number of flash memories. By detecting the number of memories and corresponding the detected value to predetermined current levels, the system optimizes current distribution to maintain reliability while supporting variable memory configurations
2Quantity of substance
If the total number of flash memories controlled by a flash memory controller is increased to increase data capacity, then the data capacity is improved, but the driving current level obtained by each flash memory decreases leading to errors in data-access operations
Solution Approach 1:
The patent adjusts the driving current parameter based on the number of flash memories to maintain adequate current levels. By detecting the number of memories and setting corresponding current levels from predetermined values, the system ensures that even when controlling many memories (e.g., 8 or more), each memory receives sufficient current to maintain operation reliability
Solution Approach 2:
The patent implements a feedback mechanism where the controller detects the number of flash memories connected and uses this information to adjust the driving current level accordingly. This closed-loop approach ensures that as data capacity increases through adding more memories, the system automatically compensates by increasing the total driving current to maintain adequate current per memory
3Device complexity
If a constant level driving current is provided to multiple flash memories, then the device complexity is reduced, but signal attenuation and noise increase when controlling more than four flash memories
Solution Approach 1:
The patent adjusts the driving current parameter to compensate for signal degradation. By increasing the current level when more flash memories are detected, the system counteracts the increased signal attenuation and noise that occur with higher memory counts, maintaining signal integrity without significantly increasing device complexity
Solution Approach 2:
The patent takes preliminary action by detecting the number of flash memories before data-access operations and pre-adjusting the driving current level to appropriate predetermined values. This preventive approach counteracts potential signal attenuation and noise issues before they affect operation reliability, rather than attempting to correct problems after they occur
Data Source
AI summary
The invention provides a flash memory controller. In one embodiment, the flash memory controller is coupled to a plurality of flash memories, and comprises a driving current generator and a processor. The driving current generator generates a driving current to drive the flash memories. The processor calculates the total number of flash memories, determines a driving current value according to the total number of flash memories, and directs the driving current generator to generate the driving current with a level greater than or equal to the driving current value. The driving current value is determined by the processor to be increased with an increase of the total number of flash memories.