Flash Memory Controller Dynamic Writing Mode
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Solution Overview
Problem
Traditional flash memory devices struggle to provide high capacity at low cost while maintaining desirable wear capacity and reliability, especially when using multi-level cells, triple-level cells, or higher-level cells.
Innovation Solution
A flash memory controller that dynamically controls the data writing mode of a flash memory module based on the amount of stored data, using a combination of one-bit-per-cell and two-bit-per-cell modes, and adjusting program threshold voltages to optimize wear capacity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cells (MLC), triple-level cells (TLC), or higher-level cells are used to provide high storage capacity at lower cost, then storage capacity and cost-effectiveness are improved, but wear capacity and reliability deteriorate
Solution Approach 1:
The patent dynamically adjusts the data writing mode between one-bit-per-cell and two-bit-per-cell modes based on the amount of stored data in the flash memory module. When the stored data amount exceeds a threshold, the system switches to one-bit-per-cell mode to improve reliability and wear capacity, while below the threshold it uses two-bit-per-cell mode to maximize storage capacity. This dynamic adaptation resolves the contradiction between storage capacity and wear capacity.
Solution Approach 2:
The patent changes the operating parameters of the flash memory cells by switching between different bit-per-cell modes (one-bit and two-bit modes). This parameter change allows the system to optimize between storage density and cell durability depending on the current storage state, thereby resolving the contradiction between high storage capacity and improved wear capacity.
2Quantity of substance
If multi-level cells (MLC), triple-level cells (TLC), or higher-level cells are used to provide high storage capacity at lower cost, then storage capacity and cost-effectiveness are improved, but reliability deteriorates
Solution Approach 1:
The system dynamically switches between two-bit-per-cell mode and one-bit-per-cell mode based on the stored data amount threshold. When the threshold is exceeded, it transitions to the more reliable one-bit mode for subsequent writes, while maintaining the ability to use two-bit mode when capacity is prioritized. This dynamic behavior resolves the reliability-capacity contradiction.
Solution Approach 2:
The patent changes the fundamental operating parameter of the flash memory from two-bit-per-cell to one-bit-per-cell mode under specific conditions (when stored data exceeds the threshold). This parameter change directly improves reliability by reducing the complexity of charge state management in each cell, at the cost of reduced storage density.
3Reliability
If one-bit-per-cell mode is used to improve wear capacity and reliability, then wear capacity and reliability are improved, but storage capacity decreases
Solution Approach 1:
The patent implements a dynamic writing mode that switches between one-bit-per-cell and two-bit-per-cell modes based on whether the stored data amount exceeds a predefined threshold. This dynamic approach allows the system to achieve high wear capacity and reliability (using one-bit mode when needed) while maintaining high storage capacity (using two-bit mode when the threshold is not exceeded), thus resolving the contradiction.
Solution Approach 2:
The system applies different data writing modes to different conditions: when the stored data amount is below the threshold, two-bit-per-cell mode is used for maximum capacity; when it exceeds the threshold, one-bit-per-cell mode is used for improved reliability. This localized application of different qualities (writing modes) to different situations resolves the contradiction between capacity and wear capacity.
4Quantity of substance
If two-bit-per-cell mode is used to maximize storage capacity, then storage capacity is improved, but wear capacity and reliability deteriorate
Solution Approach 1:
The patent employs a dynamic writing mode selection mechanism that monitors the stored data amount and switches between two-bit-per-cell mode (for maximum capacity) and one-bit-per-cell mode (for improved wear capacity). When the stored data exceeds the threshold, the system dynamically transitions to one-bit mode, thereby resolving the contradiction between maximizing storage capacity and maintaining wear capacity.
Solution Approach 2:
The system changes the operating parameter from two-bit-per-cell to one-bit-per-cell mode when the stored data amount exceeds a predefined threshold. This parameter change allows the system to achieve both high storage capacity (using two-bit mode when appropriate) and improved wear capacity (switching to one-bit mode when the threshold is exceeded).
Data Source
AI summary
A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.