Flash Memory Controller Erasure Logic
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Solution Overview
Problem
Existing memory devices face inefficiencies in data erasure and management, particularly in transitioning between operational modes and maintaining accurate status information, which affects performance and data integrity.
Innovation Solution
A memory device with a controller that utilizes a logical/physical translation table and management table to manage erasure unit areas, allowing for efficient data erasure, access, and status updates by transitioning between modes without actual data erasure, and using status update information to determine correct status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is actually erased from the erasure unit area, then data integrity is maintained, but data processing speed decreases and performance is reduced
Solution Approach 1:
The patent uses a logical/physical translation table to create a virtual mapping between logical addresses and physical addresses. When erasure is needed, the system updates the translation table to point to different physical locations rather than actually erasing data from the memory cells. This copying approach maintains data integrity through virtualization while avoiding the time-consuming actual erasure operation, thus resolving the contradiction between reliability and productivity.
2Adaptability or versatility
If the controller transitions between operational modes frequently, then data management flexibility is improved, but system complexity and error potential increase
Solution Approach 1:
The patent implements dynamic operational modes (first mode for normal operation, second mode for erasure waiting, third mode for erasure completion) that allow the controller to adapt its behavior based on the current state of the translation table and erasure unit areas. The mode transitions are managed through well-defined state changes with clear entry and exit conditions, which provides flexibility in data management while controlling system complexity through structured state machine design.
3Reliability
If the controller maintains accurate status information in the translation table, then data management reliability is improved, but memory resources and processing overhead increase
Solution Approach 1:
The logical/physical translation table serves as an intermediary data structure that maintains the mapping between logical addresses and physical addresses. This translation layer allows the controller to track the status of erasure unit areas without directly managing the complex state of each memory cell. The translation table provides a simplified view of the memory state, improving data management reliability while reducing processing overhead by avoiding direct manipulation of low-level memory status information.
Data Source
AI summary
Upon receiving an erase command and a first logical address, a controller in a first mode sets, as an erasure waiting area, an erasure unit area assigned with a first physical address associated with the first logical address in a first table. The controller in the first mode replaces, in the first table, the first physical address with a physical address assigned to an erasure completion area. The controller in a second mode sets the erasure waiting area as the erasure completion area. Upon receiving a release command to release the second mode at some point in time of data erasure from the erasure waiting area, the controller changes the operation mode to a third mode. The controller operating in the third mode erases un-erased data from the erasure waiting area and changes the operation mode from the third mode to the first mode.