Flash Memory Controller Error Bit Detection for MLC Data Integrity
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Solution Overview
Problem
The reliability of Multi Level Cell (MLC) NAND flash memory is lower than Single Level Cell (SLC) due to higher probabilities of writing errors, especially when storing multiple bits of data, which complicates ensuring correct data writing.
Innovation Solution
A data writing method and flash memory controller that includes a microprocessor unit, flash memory interface, host interface, and memory management unit to execute host write commands, detect error bits during data writing, and utilize error checking and correcting codes to ensure data integrity by managing physical blocks and pages effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC NAND flash memory is used to store multiple bits of data per memory cell, then storage capacity increases, but writing error probability increases
Solution Approach 1:
The patent segments the programming process into multiple phases (first phase for lower page, second phase for upper page) and separately manages error checking for each phase. This segmentation allows the system to handle the increased complexity of MLC multi-bit storage by breaking down the error-prone programming process into manageable stages, thereby maintaining reliability while preserving high storage capacity.
Solution Approach 2:
The patent performs error checking and correction operations during the execution of host write commands, before the data writing process is fully completed. By detecting and correcting error bits in advance during the programming phases, the system prevents erroneous data from being finalized, thus maintaining high reliability in MLC flash memory with increased storage capacity.
2Reliability
If error checking is performed during data writing, then data integrity improves, but writing speed decreases
Solution Approach 1:
The patent performs error checking and correction operations continuously during the execution of host write commands, rather than as separate post-processing steps. The memory management unit detects error bits and executes correction operations while the programming process is ongoing, ensuring data integrity without interrupting the overall writing workflow, thus maintaining writing speed while improving data integrity.
Solution Approach 2:
By performing error detection and correction during the programming phases (before the write command fully completes), the system addresses potential errors in advance. This preliminary error handling prevents rework or retries that would otherwise slow down the writing process, thereby maintaining productivity while ensuring data integrity.
Data Source
AI summary
A data writing method for writing data from a host system into a flash memory chip is provided, and the flash memory chip has a plurality of physical blocks. The method includes receiving a host writing command and write data thereof, and executing the host writing command. The method also includes giving a data program command for writing the write data into one of the physical blocks of the flash memory chip, and giving a command for determining whether data stored in the physical block has any error bit. Accordingly, the method can effectively ensure the correctness of data to be written into the flash memory chip.