Flash Memory Controller Error Origin Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory systems face reduced storage capacity and lifespan due to premature marking of good blocks as bad, caused by transient or intermittent transmission errors introduced by high-speed interfaces, which incorrectly identify data errors.
Innovation Solution
A memory controller is configured to detect error events, determine their origin, and differentiate between data and transmission errors, incrementing an error count only for data errors, and marking blocks as bad only when the count exceeds a threshold, thereby avoiding false positives and extending the usable life of memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-speed interfaces are used to increase data access speed, then productivity is improved, but transmission errors are introduced causing blocks to be marked as bad prematurely
Solution Approach 1:
The patent introduces an intermediary error detection mechanism between the high-speed interface and the block marking process. This intermediary layer analyzes error characteristics, distinguishes between transmission errors and actual data errors, and filters out transient errors before they trigger block marking. The intermediary acts as a buffer that prevents false positives from propagating to the block status management system.
Solution Approach 2:
The patent implements a feedback mechanism where error information is continuously monitored and analyzed. The system receives error signals from the high-speed interface, processes them through error detection logic, and provides feedback to determine whether block marking is appropriate. This feedback loop enables dynamic adjustment of error response based on error patterns, preventing premature block marking while maintaining data integrity.
2Reliability
If transmission errors are treated as data errors, then data integrity is protected, but storage capacity is reduced due to premature block marking
Solution Approach 1:
The patent segments the error analysis process into distinct stages: error detection, error classification, and block marking decision. By dividing the error handling process, the system can identify and separate transient transmission errors from actual data errors. This segmentation allows the system to maintain data integrity for true errors while avoiding unnecessary block marking for transient errors, thereby preserving storage capacity.
Solution Approach 2:
The patent changes the parameter of error evaluation from a binary (error present/absent) to a multi-state assessment (transient error, permanent error, transmission error, data error). This parameter transformation enables nuanced error handling where the system can respond differently based on error characteristics, protecting data integrity when needed while avoiding false block markings that would reduce storage capacity.
3Ease of operation
If error detection is simplified to improve ease of operation, then ease of operation is improved, but measurement precision of error origin is reduced
Solution Approach 1:
The patent implements a dynamic error detection approach where the complexity of error analysis adapts to the situation. For common transient errors, the system uses simple detection mechanisms that are easy to implement. For more complex error patterns, the system dynamically increases analysis depth to accurately identify error origins. This dynamic adjustment maintains ease of operation for typical cases while providing precise error origin identification when necessary.
Solution Approach 2:
The patent applies partial error detection action by focusing analysis on the most critical and common error types first. Rather than implementing comprehensive analysis for all possible error scenarios, the system performs targeted detection on high-probability error origins. This partial action approach maintains operational simplicity while achieving sufficient measurement precision for the most important error cases.
Data Source
AI summary
In one aspect, the present disclosure provides a storage device for accounting for transmission errors to improve a usable life span of memory blocks. In some embodiments, the storage device includes: a memory array including a plurality of memory blocks; and a memory controller in communication with the memory array via an interface, wherein the memory controller is configured to detect an error event associated with data from one of the plurality of memory blocks; determine an origin of the error event; increment an error count if the origin of the error event indicates a data error in the one of the plurality of memory blocks and not if the origin of the error event indicates a transmission error; compare the error count to a threshold value; and mark the one of the plurality of memory blocks as bad when the error count exceeds the threshold value.