Flash Memory Controller Transmission History Buffering

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Solution Overview

Problem

Conventional flash memory controllers face errors and poor transmission quality due to discrepancies in command signal timing and order between hardware components, leading to erroneous transmissions across the communication interface.

Innovation Solution

A flash memory controller with a processor, input/output circuit, and control logic circuit that buffers and records transmission history information, including command and address data, to ensure accurate sequencing and timing of signals, using a specific communication interface to store and retrieve this information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If command signals are handled by different hardware components in conventional flash memory controllers, then processing capability is improved, but transmission timing accuracy deteriorates

Engineering Contradiction:

Improveprocessing capabilityVSAvoidtransmission timing accuracy

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by recording the actual transmission history of command signals before any errors can occur. The flash memory device stores the sequence of command signals, address information, and data I/O operations in a buffer memory during normal operation. This recorded history is then used for debugging and analysis, allowing the system to maintain high processing capability while providing a mechanism to verify and correct timing accuracy issues.

Inventive Principle:

Principle #10Preliminary action

2Speed

If clock timing is accelerated to meet faster transmission requirements, then transmission speed is improved, but error frequency increases

Engineering Contradiction:

Improvetransmission speedVSAvoiderror frequency

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent implements feedback by recording the actual transmission history including command signals, address information, and data I/O operations that occur during high-speed transmission. This feedback mechanism allows the system to monitor transmission quality and identify errors that occur during accelerated clock timing operations, enabling debugging and correction while maintaining high transmission speeds.

Inventive Principle:

Principle #23Feedback

3Productivity

If transmission speed is increased to meet current clock timing requirements, then productivity is improved, but transmission reliability deteriorates

Engineering Contradiction:

Improvetransmission speedVSAvoidtransmission reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-recording the complete transmission history including command signals, address information, and data I/O operations in a buffer memory during high-speed transmission. This recorded information is available before any debugging or error analysis is needed, allowing the system to maintain high productivity while providing comprehensive data for verifying transmission reliability.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12105992B1Flash memory mechanism capable of storing and recording actual transmission history information of communication interface between flash memory controller and flash memory device

Publication Date: 2024.10.01 SILICON MOTION INC

AI summary

A method of a flash memory controller includes: using a processor to issue and generate a command signal into a control logic circuit though a bus; buffering the command signal in a specific queue of a specific channel controller of the I/O circuit; and using the arbitrator to control the specific buffer storing a first transmission history information of the specific communication interface.