Flash Memory Controller Interruption Protection
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Solution Overview
Problem
In semiconductor devices with multiple masters accessing a shared flash memory, important writing/erasing processes can be interrupted, leading to instability and increased processing time, as other masters cannot access the flash memory during these operations.
Innovation Solution
A memory controller is configured to prohibit interruptions of ongoing writing/erasing processes by other masters, using specific commands to ensure that important data operations are not interrupted, thereby maintaining system stability and reducing processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a writing/erasing process for flash memory is interrupted to allow other masters to access the flash memory, then other masters can access the flash memory during writing/erasing operations, but the writing/erasing process may be interrupted halfway through, causing system instability
Solution Approach 1:
The memory controller acts as an intermediary between multiple masters and the flash memory. It manages access requests from multiple masters, determines whether to interrupt or wait based on the state of ongoing operations, and controls the actual access to flash memory. This intermediary role resolves the contradiction by coordinating access to prevent instability while maintaining efficiency.
Solution Approach 2:
The system dynamically adjusts its behavior based on the state of flash memory operations. When a writing/erasing process is detected, the memory controller dynamically decides whether to allow interruption or wait, rather than following a fixed access protocol. This dynamic adaptation enables the system to balance between allowing concurrent access and preventing instability.
2Reliability
If other masters wait for writing/erasing processes to complete before accessing flash memory, then system stability is maintained, but other masters experience long waiting times
Solution Approach 1:
The memory controller changes the parameter of access permission based on the operation state. When the flash memory is in a writing/erasing state, the controller changes the access parameter from 'allow interrupt' to 'wait' for protected operations, and from 'wait' to 'allow interrupt' for non-protected operations. This parameter change enables flexible time management that reduces waiting time while maintaining stability.
3Productivity
If the memory controller allows interruption of writing/erasing processes, then other masters can access flash memory during operations, but important data processes may be interrupted causing system instability
Solution Approach 1:
The memory controller applies different access control policies to different operations locally. Protected operations (writing/erasing) receive special treatment with interruption restrictions, while non-protected operations allow interruption. This local differentiation of access quality enables the system to maintain stability for critical operations while allowing efficiency for non-critical operations.
Data Source
AI summary
According to one embodiment, a memory controller is configured so that when the memory controller controls a writing/erasing process for a flash memory performed by a first or second master, the memory controller can prohibit, while the first master is performing the writing/erasing process for the flash memory, an interruption of the writing/erasing process in execution, the interruption resulting from access to the flash memory by the second master.