Flash Memory Controller LLR Mapping Table Update
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Solution Overview
Problem
The threshold voltage distribution in flash memory cells changes due to increased program/erase cycles and retention time, leading to incorrect data retrieval and higher error rates when using original control gate voltage settings.
Innovation Solution
A flash memory controller method that reads a logical page using multiple sets of threshold voltages (original, positively adjusted, and negatively adjusted) to obtain different readout information, which is then decoded to generate a Log Likelihood Ratio (LLR) mapping table for accurate data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If original control gate voltage settings are used for reading flash memory cells, then the read operation is simple and fast, but the data retrieval accuracy deteriorates due to threshold voltage distribution changes from increased P/E cycles and retention time
Solution Approach 1:
The patent applies preliminary action by performing threshold voltage adjustment and LLR mapping table updates before actual data reading operations. The controller pre-calculates adjusted threshold voltages based on P/E cycle counts and retention times, and pre-generates updated LLR mapping tables using read-disturbance-aware algorithms. This preparation ensures accurate data retrieval without adding complexity during the actual read operation.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting control gate voltage thresholds based on the flash memory cell's P/E cycle history and retention time. The controller modifies threshold voltage parameters and updates LLR mapping table parameters to compensate for threshold voltage distribution shifts. This allows the system to maintain high data retrieval accuracy despite changes in memory cell characteristics over time.
2Measurement precision
If multiple sets of threshold voltages are used to read the same logical page, then the decoding accuracy improves through multiple readout information samples, but the read operation time increases
Solution Approach 1:
The patent applies partial action by selectively using multiple threshold voltage sets only when needed for accurate decoding. The controller first attempts decoding with standard threshold voltages, and only invokes additional threshold voltage sets when initial decoding fails or confidence levels are low. This approach achieves high decoding accuracy while minimizing the time penalty of multiple read operations.
Solution Approach 2:
The patent implements feedback mechanisms where the controller monitors decoding results and uses this information to determine whether additional read operations with adjusted threshold voltages are necessary. The system feeds back decoding confidence metrics and error rates to dynamically decide on subsequent read operations, optimizing the balance between decoding accuracy and read time.
3Reliability
If the LLR mapping table is updated based on readout information from multiple threshold voltage readings, then the probability of successful decoding for subsequent operations improves, but the processing complexity and memory resources increase
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing multiple LLR mapping tables corresponding to different threshold voltage conditions. Instead of computing updated mapping tables in real-time during read operations, the controller pre-generates these tables based on historical P/E cycle data and retention time characteristics, storing them in memory for rapid lookup during decoding operations. This reduces processing complexity while maintaining high decoding success probability.
Solution Approach 2:
The patent implements dynamic LLR mapping table management where the controller selects and updates mapping tables based on current flash memory conditions. The system dynamically adjusts which mapping table to use based on P/E cycle counts, retention time, and observed error patterns. This dynamic approach optimizes decoding reliability while managing processing complexity through intelligent table selection and incremental updates.
Data Source
AI summary
The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read a first logical page of a physical page of the flash memory module to obtain first readout information, second readout information and third readout information, respectively; decoding the first readout information, the second readout information and the third readout information to generate decoded data of the first logical page; and generating a LLR mapping table according to the decode data of the first logical page, the first readout information, the second readout information and the third readout information, for use when reading and decoding other logical pages.