Flash Memory Controller LLR Table Update for BER Reduction
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Solution Overview
Problem
The bit error rate (BER) in flash memory controllers degrades over time due to physical non-uniformity and changes in reference voltages caused by fabrication processes, temperature, and programming cycles, limiting the effectiveness of pre-defined log likelihood ratio (LLR) values in error-correcting codes.
Innovation Solution
A method is introduced to periodically measure and update LLR values in an LLR table within the flash memory controller, ensuring high decoding success and low BER by adapting to changes in the number of program-and-erase cycles and using a histogram-based approach to determine new LLR values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-defined LLR values are used in the LLR table, then the device complexity is reduced and ease of operation is improved, but the reliability degrades over time due to physical non-uniformity and voltage changes
Solution Approach 1:
The LLR table is transformed from a static pre-defined structure to a dynamic one that is periodically updated based on measured cell voltage distributions. The processor automatically recalculates LLR values when triggered by program-erase cycle counters or decoding failure detections, allowing the system to adapt to changing physical conditions while maintaining operational simplicity through automated updates.
Solution Approach 2:
The system implements feedback mechanisms where decoding failures and measured cell voltage distributions are used to trigger LLR table updates. When decoding failures occur or when the processor detects changes in voltage distributions, it automatically initiates remeasurement and reconstruction of LLR values, creating a closed-loop system that continuously improves reliability based on actual performance feedback.
2Reliability
If LLR values are updated periodically based on program-and-erase cycles, then the reliability is maintained over time, but the loss of time increases due to periodic measurement and update operations
Solution Approach 1:
The system performs LLR table updates periodically based on program-erase cycle counters rather than continuously. The processor is triggered to remeasure and update LLR values at predetermined intervals (e.g., every 1000 P/E cycles) or when specific thresholds are reached, balancing the need for reliability maintenance with minimization of time loss by avoiding unnecessary continuous updates.
Solution Approach 2:
The system performs preliminary LLR measurements and updates during idle periods or between normal read/write operations. By proactively updating LLR values before decoding failures occur (based on predicted P/E cycle thresholds), the system prevents performance degradation without interrupting normal operations, thus reducing actual time loss.
3Measurement precision
If multiple reference voltages are provided for MLC/TLC flash memory, then the measurement precision of cell voltage detection is improved, but the device complexity increases due to voltage generation and management
Solution Approach 1:
The flash memory controller is designed with multi-functional voltage generation capabilities that can provide multiple reference voltages (Vref0, Vref1, Vref2) for reading different bit levels in MLC and TLC cells. The same controller hardware that manages data read/write operations also generates and manages these reference voltages, eliminating the need for separate dedicated voltage generation circuits and reducing overall system complexity.
Data Source
AI summary
Log likelihood ratio (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.