Flash Memory Controller Low Standby Current Mode
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Solution Overview
Problem
Current flash memory storage apparatuses face challenges in reducing standby current consumption and wake-up time, with deep power down mode requiring significant time to wake up and normal standby mode consuming higher current due to operational voltage needs.
Innovation Solution
A flash memory storage apparatus with a memory controller circuit and memory cell array that operates in multiple modes, including a low standby current mode, where the memory controller controls the apparatus to enter and exit this mode via commands, reducing power consumption and wake-up time by blocking power supply to unnecessary components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the flash memory storage apparatus enters deep power down mode to reduce current consumption, then the current consumption is very low, but the wake-up time becomes considerable and long
Solution Approach 1:
The patent introduces a new operational state (low standby current mode) that dynamically adjusts the power consumption level between deep power down mode and normal standby mode. The memory controller can selectively enter this intermediate state based on system requirements, providing a dynamic solution that balances power savings with wake-up speed needs.
Solution Approach 2:
The patent changes the operational parameters by introducing a new mode with specific current consumption characteristics that differ from both deep power down mode and normal standby mode. This parameter change creates a new operating point that optimizes both power consumption and wake-up time simultaneously.
2Loss of time
If the flash memory storage apparatus operates in normal standby mode to reduce wake-up time, then the wake-up time is shorter, but the current consumption becomes higher
Solution Approach 1:
The low standby current mode provides a dynamic operational state that can be selected based on system needs. When long wake-up time is acceptable, the system enters this mode for better power savings. When fast wake-up is needed, the system can transition to normal standby mode, creating a dynamic power management strategy.
Solution Approach 2:
By introducing a new operational mode with distinct current consumption characteristics, the patent creates additional parameter options for system optimization. This parameter expansion allows the system to achieve better power efficiency without being constrained to the trade-off between deep power down mode and normal standby mode.
3Loss of time
If the voltage generator circuit operates to provide high voltage to word line decoder circuit in normal standby mode, then the wake-up time is shorter, but the current consumption increases and cannot be effectively reduced
Solution Approach 1:
The patent extracts the voltage generator circuit operation from the normal standby mode by introducing a new low standby current mode where the voltage generator is turned off. This extraction allows the system to achieve lower power consumption while maintaining acceptable wake-up performance through the intermediate operational state.
Data Source
AI summary
A flash memory storage apparatus having a plurality of operation modes is provided. The flash memory storage apparatus includes a memory controller circuit and a memory cell array. The memory controller circuit is configured to control the flash memory storage apparatus to operate in one of the operation modes. The operation modes include a low standby current mode. The memory cell array is coupled to the memory controller circuit. The memory cell array is configured to store data. The data includes read-only memory data. The memory controller circuit controls the flash memory storage apparatus to enter the low standby current mode according to a first command. The memory controller circuit wakes up the flash memory storage apparatus from the low standby current mode according to a second command. When the flash memory storage apparatus operates in the low standby current mode, the read-only memory data is kept.