Flash Memory Controller Multi-Plane Access Simplification
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Solution Overview
Problem
Conventional flash memory devices require complex command sequences and longer waiting times to access multiple planes, complicating operations such as data read, write, and erase operations.
Innovation Solution
A flash memory device and controller system with an I/O control circuit, command register, data register, and control circuit that perform a data toggle operation to sequentially transmit data units from multiple planes using a single command sequence, simplifying the communication process and reducing waiting times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple command sequences are used to access multiple planes, then data access capability is improved, but command sequence complexity increases and waiting time increases
Solution Approach 1:
The patent combines multiple plane access operations into a single command sequence. The control circuit receives one command sequence containing address information for multiple planes, automatically generates corresponding address information for each plane, and sequentially performs read operations on all planes without requiring separate command sequences for each plane, thereby reducing command complexity while maintaining multi-plane access capability
Solution Approach 2:
The control circuit is designed with multi-functionality to handle multiple planes through a unified command interface. It can parse a single command sequence to extract address information for multiple planes, automatically generate the necessary address variations, and coordinate sequential access across all planes, making the system capable of handling diverse plane access requirements through a single standardized command structure
2Productivity
If multiple command sequences are used to access multiple planes, then data access capability is improved, but waiting time increases
Solution Approach 1:
The control circuit performs preliminary actions by pre-generating all necessary address information for multiple planes within the control circuit itself before actual data read operations begin. This eliminates the need for the host controller to sequentially issue multiple command sequences with intermediate waiting periods, as all address preparation is completed in advance, allowing continuous sequential access to all planes
Solution Approach 2:
The system maintains continuity of useful action by enabling the control circuit to sequentially access multiple planes without interrupting the command flow. Once a single command sequence is issued, the control circuit continuously performs read operations on each plane in sequence without requiring the host to wait or issue additional commands between plane accesses, eliminating idle waiting time and maintaining continuous data retrieval
3Productivity
If multiple command sequences are used to access multiple planes, then comprehensive plane access is achieved, but operation simplicity deteriorates
Solution Approach 1:
The control circuit implements self-service functionality by autonomously generating address information for multiple planes based on a single received command sequence. Instead of requiring the host controller to manually prepare and send separate address information for each plane through multiple command sequences, the control circuit automatically derives and manages all necessary address variations, simplifying the host's operation while ensuring comprehensive plane access
Data Source
AI summary
A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.