Flash Memory Controller Multi-Plane Data Toggle Command

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Solution Overview

Problem

Conventional flash memory devices require complex command sequences and longer waiting times for multiple plane operations due to the need for separate read commands for each plane, complicating data communication and processing.

Innovation Solution

A flash memory device and controller system that uses an I/O control circuit, command register, and control circuit to perform a data toggle operation, allowing sequential transmission of data units from multiple planes in response to a single read or data toggle command, simplifying command sequences and reducing waiting times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple separate read commands are issued to read data from multiple planes, then data from each plane can be read, but the command sequence becomes more complicated and waiting time increases

Engineering Contradiction:
Improvedata reading completenessVSAvoidcommand sequence complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple plane read operations into a single read command by introducing a plane selection mechanism. The flash memory device can sequentially output data from multiple planes (e.g., D0 plane, D1 plane, D2 plane, D3 plane) in response to one read command, eliminating the need for separate commands for each plane and simplifying the command sequence while maintaining complete data reading capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic plane selection and data output control within the flash memory device. The device can dynamically switch between different planes (D0-D3) and control the output timing of data from each plane, allowing flexible data retrieval from multiple planes without requiring static separate commands for each plane

Inventive Principle:
Principle #15Dynamics

2Reliability

If multiple separate read commands are issued to read data from multiple planes, then data from each plane can be read, but waiting time period increases

Engineering Contradiction:
Improvedata reading completenessVSAvoidwaiting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent enables continuous data output from multiple planes in response to a single read command. The flash memory device sequentially outputs data from D0 plane, then D1 plane, D2 plane, and D3 plane without requiring the controller to wait for each plane individually, maintaining continuous useful action and reducing total waiting time while ensuring complete data reading

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The patent performs preliminary organization of multi-plane data within the flash memory device before output. The device prepares and buffers data from multiple planes internally, then outputs it sequentially in response to one read command, eliminating the need for the controller to issue multiple commands and reducing waiting time while ensuring all data is read

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11977776B2Flash memory controller and method capable of sending read command or data toggle command to ask for flash memory device return more plane data of different planes
Publication Date: 2024.05.07 SILICON MOTION INC
  • US11977776B2 patent drawing
  • US11977776B2 patent drawing
  • US11977776B2 patent drawing

AI summary

A flash memory device is disclosed. The memory cell array has a first plane and a second plane and stores a first data unit and a second data unit. The data register buffers the first data unit and the second data unit transmitted from the memory cell array when a read command or a data toggle command is received and stored by the command register. The control circuit performs a data toggle operation to control the data register selecting and transferring the first data unit and the second data unit to the I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through a specific communication interface in response to the read command or the data toggle command. The transmission of the first data unit is followed by the transmission of the second data unit.