Flash Memory Controller Over-Erased Cell Recovery
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Solution Overview
Problem
Conventional flash memory devices face challenges in quickly recovering over-erased memory cells without adversely affecting normal cells, due to shared bit lines and time-consuming post-program operations.
Innovation Solution
A flash memory device with a memory controller that applies negative voltage to common bulk and source lines and positive voltage to word lines of over-erased cells, using a Fowler-Nordheim post-programming operation in block-based units, while floating bit lines to prevent influence on non-over-erased cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional post-program operation applies drain voltage to the bit line, then over-erased memory cells can be recovered, but normal cells that are not over-erased are adversely affected
Solution Approach 1:
The patent divides the memory array into multiple memory blocks, each with independent bulk lines and source lines. This segmentation allows the post-program operation to be applied to only the specific memory block containing over-erased cells, rather than affecting all blocks through shared bit lines. The isolation is achieved by having separate bulk and source line control for each block.
Solution Approach 2:
The patent applies different voltage conditions to different regions: negative voltage to the bulk line and source line of the selected memory block, positive voltage to word lines coupled to over-erased cells, and floating bit lines. This localized voltage application ensures that only the targeted over-erased cells undergo the post-program operation while normal cells in the same block and cells in other blocks remain unaffected.
2Reliability
If the conventional post-program operation is performed according to bit line unit, then over-erased cells can be recovered, but the operation requires a long time to complete
Solution Approach 1:
The patent merges multiple bit line operations into a single block-based operation. By applying voltages to the common bulk line and source line of an entire memory block simultaneously, the post-program operation can recover all over-erased cells in that block in parallel, rather than processing each bit line sequentially. This significantly reduces the total operation time.
Solution Approach 2:
The patent transitions from a one-dimensional bit line-based recovery approach to a two-dimensional block-based approach by utilizing the bulk line and source line dimensions. This allows simultaneous control of multiple cells across different bit lines through the common bulk and source lines, enabling parallel processing and reducing operation time.
3Device complexity
If the flash memory device uses shared bit lines for multiple cells, then device complexity is reduced, but the post-program operation cannot selectively recover only over-erased cells
Solution Approach 1:
The patent introduces bulk lines and source lines as intermediary control elements between the control logic and the memory cells. These intermediaries provide an additional control dimension that enables selective recovery operations. By controlling the bulk and source lines, the system can target specific memory blocks and cells without requiring separate bit lines for each cell, thus maintaining structural simplicity while achieving selective recovery.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method efficiently recovers over-erased memory cells quickly and prevents adverse effects on normal cells, enhancing the reliability and speed of the flash memory device.
Implementation Method 1
a Fowler-Nordheim (FN) post-programming operation is used for recovering the over-erased memory cells
Data Source
AI summary
This invention introduces a flash memory device and a method which are capable of quickly recovering the over-erased memory cells while preventing adverse influence to normal cells that are not over-erased. The flash memory device comprises a memory array and a memory controller coupled to the memory array. The memory controller is configured to select a memory block which comprises at least one over-erased memory cell. The memory controller is further configured to apply a negative voltage to the common bulk line and the common source line of the selected memory block. The memory controller is further configured apply a positive voltage to word lines that are coupled to the at least one over-erased memory cell in the selected memory block, and apply the positive voltage to word lines that are not coupled to any one of the at least one over-erased memory cell in the selected memory block.