Flash Memory Controller Logical Unit Mapping for Page Capacity Utilization

The patent merges multiple small data units (4KB write operations from different logical access addresses) into a single physical page (8KB) by maintaining a write buffer that accumulates data from multiple logical pages. When the buffer reaches sufficient capacity, the accumulated data is written together as a single unit to one physical page, thereby combining multiple scattered write operations into one consolidated physical write operation that fully utilizes the physical page capacity.

The patent implements a dynamic write buffer management mechanism that adapts its behavior based on buffer occupancy levels. When the write buffer contains sufficient data, the controller consolidates and writes to physical pages to maximize capacity utilization. When the buffer is insufficient or latency constraints arise, the controller can flush data immediately. This dynamic adjustment allows the system to balance between capacity optimization and latency reduction based on real-time conditions.

The patent introduces a write buffer as an intermediary layer between the logical unit mapping table and the physical pages. The mapping table maintains the relationship between logical access addresses and physical pages, while the write buffer temporarily holds data from multiple logical addresses before consolidation. This intermediary buffer simplifies the mapping management by decoupling the logical-to-physical mapping from the actual write operation, allowing the system to handle complex multi-address writes without requiring the mapping table to directly manage every detail of data consolidation.