Flash Memory Controller Parity Signal DDR Transmission
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Solution Overview
Problem
NAND flash memory devices experience signal integrity issues and bit errors during high-speed data transmission in double data rate (DDR) mode, leading to decreased storage reliability.
Innovation Solution
A memory system that dynamically uses a write enable signal as a parity check bit for data transmission in DDR mode, with a memory controller generating a parity signal and a bit error detection unit in the flash memory device performing parity checks to identify and retransmit data in case of errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted in DDR scheme, then transmission speed is improved, but signal integrity deteriorates and bit errors occur
Solution Approach 1:
The patent applies preliminary action by generating a parity bit before data transmission in the memory controller, and by preparing to perform parity checking before data is written to the flash memory device. This advance preparation of error detection mechanisms allows the system to maintain high-speed DDR transmission while having error detection ready to catch any signal integrity issues that may occur during transmission.
2Productivity
If write enable signal is used for DDR data input, then data transmission capability is improved, but error detection capability deteriorates
Solution Approach 1:
The patent implements multi-functionality by making the write enable signal serve dual purposes: it controls the timing and enablement of data input during DDR transmission, and simultaneously functions as a parity check bit for error detection. The flash memory device checks the write enable signal to detect transmission errors while still allowing high-speed data input through the same signal line, thus achieving both productivity and measurement precision.
3Reliability
If parity check is implemented, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by utilizing existing components within the memory controller and flash memory device to perform parity checking. The memory controller generates the parity bit using its existing logic, and the flash memory device uses its existing read/write circuitry to perform the parity check on the write enable signal. No separate dedicated error detection hardware is required, as the system's existing components serve the additional function of error detection, thereby improving reliability without significantly increasing device complexity.
Data Source
AI summary
A memory system is provided. In the memory system, a memory controller transmits a write enable signal and a data strobe signal to a flash memory device, a command or an address is transmitted at a rising edge or a falling edge of the write enable signal through a data line in a single data rate (SDR) scheme, and input data is transmitted at each of a rising edge and a falling edge of the data strobe signal through the data line in a double data rate (DDR) scheme. The memory controller includes a parity signal generation unit configured to receive the write enable signal transmitted in the DDR scheme and output a parity signal by generating a first parity bit for the input data. The flash memory device includes a bit error detection unit configured to receive the parity signal output from the memory controller, generate a second parity bit for the input data received by the flash memory device, and determine whether a bit error has occurred to the input data by performing a parity check.