Flash Memory Controller for Volatile Data Preservation During Power Outages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing solutions for preserving volatile memory contents during power outages, such as NVRAM, are expensive due to the need for specialized batteries and components, and can lead to data inconsistency or irretrievability when NVRAM is remote from the processor or difficult to access when located proximate to the processor.
Innovation Solution
Employing flash memory with a controller and a low-cost alternative power source, such as a battery or supercapacitor, to automatically transfer data from volatile memory to non-volatile flash memory during power failures, allowing for easy data recovery when power is restored, and using commodity components to keep costs low.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NVRAM with specialized battery is used to preserve volatile memory contents, then data integrity during power outage is improved, but system cost increases significantly
Solution Approach 1:
The patent replaces expensive specialized NVRAM batteries with conventional, inexpensive batteries. The patent acknowledges that conventional batteries will exhaust power faster than specialized batteries, but this is acceptable because the system uses flash memory which can retain data without power, and the faster battery depletion means the battery will be replaced more frequently but at lower cost. This principle resolves the contradiction by accepting shorter duration (faster battery exhaustion) in exchange for significantly lower cost.
Solution Approach 2:
The patent changes the battery capacity parameter to match conventional battery specifications rather than specialized high-capacity battery requirements. By using conventional batteries with different capacity characteristics, the system achieves cost reduction while maintaining adequate power supply for the critical data preservation function during typical power outage scenarios.
2Duration of action of moving object
If battery must provide large amount of power for extended period, then data preservation capability is improved, but battery cost and engineering complexity increase
Solution Approach 1:
The patent accepts that conventional batteries will provide shorter power duration compared to specialized batteries, but this is compensated by the use of flash memory which preserves data without requiring continuous power. The shorter battery lifespan is acceptable because batteries are replaced frequently at low cost, and the engineering complexity of designing high-capacity batteries is avoided.
Solution Approach 2:
The patent introduces flash memory as an intermediary between volatile memory and permanent storage. This intermediary allows data to be preserved during power outages without requiring the battery to provide extended power, because the flash memory acts as a bridge that can be written to during brief power availability and retains data without continuous power supply.
3Ease of operation
If NVRAM is located remote from processor, then data accessibility during power failure is improved, but data consistency and reliability deteriorate
Solution Approach 1:
The patent uses flash memory as an intermediary component that is positioned strategically to receive data from the processor during normal operation and retain it during power outages. This intermediary allows the system to achieve both data consistency (through controlled write operations during power availability) and accessibility (through the flash memory storage capability).
4Reliability
If NVRAM is located proximate to processor, then data consistency is improved, but data retrievability during system failure deteriorates
Solution Approach 1:
The patent segments the data preservation function into two distinct components: volatile memory for active processing near the processor, and flash memory for data retention that can be independently accessed. This segmentation allows data consistency to be maintained through controlled writes during normal operation, while data retrievability is ensured through the independent accessibility of flash memory even when the processor or motherboard fails.
Solution Approach 2:
The patent positions flash memory as an intermediary between the processor and permanent storage, creating a data retention layer that is physically separate from the processor but logically connected. This intermediary structure ensures that data can be written consistently during normal operation while remaining retrievable through the flash memory interface even when the processor fails or the motherboard must be replaced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively preserves volatile memory contents during power outages using low-cost components, ensuring data integrity and accessibility without the need for expensive specialized batteries, and allows for easy relocation of data recovery.
Implementation Method 1
a low-cost alternative power source, such as a battery or supercapacitor
Implementation Method 2
a low-cost alternative power source, such as a battery or supercapacitor
Data Source
AI summary
A method and apparatus for preserving contents of a volatile memory when a main (e.g., AC) power source is disconnected. The apparatus comprises flash memory, a controller for writing to the flash memory and a temporary power source. The temporary power source may be a relatively low power battery or supercapacitor. The apparatus is removably attached to a computing device (e.g., via a USB port). When main power of the device is disconnected, the temporary power source provides power for the apparatus, the volatile memory containing data to be safeguarded, and sufficient processing resources to transfer the data. For example, an auxiliary processor may be powered (instead of a relatively high-power processor) or just one core of a multi-core processor. Data are written to the apparatus and can be recovered when main power is reconnected. Or, the apparatus may be detached and attached to a different device for data recovery.