Flash Memory Controller Logical Block Priority Caching
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Solution Overview
Problem
In flash memory systems, identifying the correct physical block and page for data access from a host system is inefficient, leading to suboptimal access times due to the need for frequent conversions between logical and physical addresses.
Innovation Solution
A memory controller with a block management unit, physical page identifying unit, logical block information holding unit, priority order management unit, and control unit that efficiently manages and prioritizes logical block information to directly access physical blocks and pages based on access requests, optimizing the relationship between logical and physical addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If logical block to physical block conversion is performed for every access request, then address translation accuracy is maintained, but access time increases
Solution Approach 1:
The patent applies preliminary action by pre-translating logical block addresses to physical block addresses and storing them in a translation cache before actual access requests arrive. When an access request comes in, the controller first checks the cache for pre-translated addresses, avoiding repeated translation operations and reducing access time while maintaining accuracy through cache validation mechanisms
2Productivity
If physical page identification is performed for every write operation, then data writing accuracy is ensured, but writing efficiency decreases
Solution Approach 1:
The patent applies preliminary action by pre-identifying and caching the physical page with the smallest page number among free pages in each physical block before write operations commence. This pre-identified page information is stored in a page cache, allowing the controller to quickly retrieve the correct write destination without performing repeated identification operations, thus improving writing efficiency while maintaining accuracy through cache consistency management
Solution Approach 2:
The patent applies copying by creating and maintaining a cached copy of physical page identification information (specifically the smallest page number among free pages) separate from the actual flash memory structure. This copy allows rapid access to write destination information without repeatedly querying the actual flash memory page status, improving writing efficiency while the cache is kept synchronized with the actual state to ensure accuracy
Data Source
AI summary
The object of the present invention is to efficiently perform access to a physical block corresponding to a logical block often designated by an access request. To realize it, predetermined number of pieces of logical block information each for access to a physical block corresponding to logical block, until then, designated by an access request is held. In holding the predetermined pieces of logical block information, a piece of logical block information having high priority precede a piece of logical block information having low priority in priority order. In management of the priority order, priority of a piece of logical block information corresponding to a logical block often designated by an access request becomes high. When an access request is received, if logical block information corresponding to the logical block designated by the access request is held, access to the physical block corresponding to the designated logical block is performed based on the held logical block information.