Flash Memory Controller Programming Parameter Adjustment
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Solution Overview
Problem
Flash memory devices experience increased bit error rates and reliability degradation due to the accumulation of charge traps during program/erase cycles, leading to a variable threshold voltage window and variance, which affects the number of errors as the cycle count increases, making it challenging to maintain a constant bit error rate.
Innovation Solution
A flash memory device with a controller that adjusts programming parameters based on cycle count indications, including setting a variable threshold voltage window and target threshold voltages, to maintain a consistent bit error rate by increasing the threshold voltage window as the cycle count increases, thereby reducing the impact of charge traps and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed voltage programming and erase operations are used, then the programming window remains fixed, but the threshold voltage margin between program and erase levels decreases significantly due to charge trap accumulation
Solution Approach 1:
The patent applies dynamics by making the programming voltage and erase voltage variable rather than fixed. The programming voltage is adjusted based on the number of program/erase cycles performed, increasing as cycle count increases. Similarly, the erase voltage is dynamically adjusted based on cycle count. This dynamic adjustment compensates for charge trap accumulation and maintains adequate threshold voltage margins throughout the device lifecycle.
Solution Approach 2:
The patent changes the voltage parameters (programming voltage and erase voltage) as a function of program/erase cycle count. By modifying these electrical parameters dynamically, the system compensates for degradation effects and maintains reliable operation across the full range of expected cycle counts.
2Reliability
If program and verify or erase and verify mechanisms are used to achieve correct voltage margin, then the voltage margin is maintained, but the cycle count increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal programming voltages and erase voltages for different program/erase cycle counts. Instead of performing iterative verify operations to determine the correct voltage margin, the system uses the pre-determined voltage values from lookup tables, eliminating the need for repeated verify cycles and significantly reducing total operation time.
Solution Approach 2:
The patent introduces lookup tables as an intermediary between the controller and the programming/erasing operations. These tables store pre-computed voltage values that map cycle counts to optimal programming and erase voltages. This intermediary structure allows the system to quickly retrieve appropriate voltage parameters without performing complex real-time calculations or iterative verify operations.
3Reliability
If the threshold voltage window is increased to compensate for charge traps, then the bit error rate decreases, but the device complexity increases due to variable parameter management
Solution Approach 1:
The patent uses lookup tables as an intermediary to manage the complexity of variable parameter management. Instead of requiring complex real-time calculations or sophisticated control algorithms, the system simply retrieves pre-computed voltage values from lookup tables based on the current cycle count. This approach maintains reliability through variable voltage adjustment while keeping the controller implementation relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the effect of charge traps, increases the reliability of flash memory units, and allows for higher cycle counts with a lower bit error rate, enabling the flash memory device to operate reliably across its lifespan with a constant bit error rate.
Implementation Method 1
There are currently three common methods of programming Flash memory: channel electron ejection, Fowler-Nordhiem (F-N) tunneling from the source or drain, and F-N tunneling from the channel.
Implementation Method 2
During program or erase the Flash cell is subject to high electric field to support oxide tunneling and hot electron injection.
Implementation Method 3
During program or erase the Flash cell is subject to high electric field to support oxide tunneling and hot electron injection.
Data Source
AI summary
A flash memory module and a method for programming a page of flash memory cells, the method includes: receiving a cycle count indication indicative of a number of program cycles of the page of memory cells; setting a value of a programming parameter of a programming operation based on the cycle count indication; and programming at least one flash memory cell of the page of flash memory cells by performing the programming operation.