Flash Memory Controller Read Disturbance Mitigation via Error-Based Data Relocation
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Solution Overview
Problem
Flash memory devices, particularly TLC and QLC blocks, suffer from read disturbance issues leading to data degradation and increased bit error rates when frequently accessed, causing system performance degradation and subsequent read disturbances in new blocks.
Innovation Solution
A flash memory controller method that selects blocks based on bit error rates, moving data with lower error rates into SLC blocks and data with higher error rates into QLC blocks, optimizing page distribution to minimize read disturbance and maintain storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is moved to another TLC/QLC block when read disturbance occurs, then data quality is temporarily improved, but the read disturbance issue quickly recurs on the new block
Solution Approach 1:
The patent segments the flash memory into different block types (TLC blocks and SLC blocks) with different characteristics. SLC blocks are used as intermediate storage with higher reliability, while TLC blocks are used for normal storage. This segmentation allows data to be moved to appropriate block types based on their error rates and access patterns, preventing read disturbance recurrence.
Solution Approach 2:
The patent changes the block type parameter (from TLC to SLC) when data experiences read disturbance. By monitoring bit error rates and changing the storage medium parameter, the system adapts data placement dynamically. SLC blocks have better read disturbance resistance, so moving affected data to SLC blocks changes the physical parameters of storage to improve reliability.
2Productivity
If data is frequently accessed in TLC/QLC blocks, then system performance is improved through fast access, but read disturbance causes data degradation and increased bit error rates
Solution Approach 1:
The patent introduces SLC blocks as an intermediary storage layer between the host and TLC blocks. When TLC blocks experience read disturbance, data is moved to SLC blocks which act as a buffer or intermediary. This intermediary layer protects the original TLC data while maintaining system performance, as SLC blocks can handle frequent reads without degradation.
Solution Approach 2:
The patent implements dynamic data placement where data is moved between TLC and SLC blocks based on real-time conditions such as bit error rates and access patterns. This dynamic adjustment allows the system to optimize between performance and reliability continuously, rather than using a fixed storage scheme.
3Ease of operation
If multiple read operations are performed on the same block, then data is readily accessible, but the block suffers from read disturbance causing lower data quality
Solution Approach 1:
The patent performs preliminary actions by monitoring bit error rates and proactively moving data before severe degradation occurs. The system detects early signs of read disturbance through error rate monitoring and preemptively relocates data to SLC blocks, preventing quality degradation before it significantly impacts data accessibility.
Data Source
AI summary
The present invention provides a control method of a flash memory controller wherein the control method includes the steps of: selecting a first block; reading pages of the first block and determining a bit error rate or a bit error count of each page; for each of the pages, if the bit error rate or the bit error count of the page is not greater than a first threshold value, moving the data of the page into a second block; and for each of the pages, if the bit error rate or the bit error count of the page is greater than the first threshold value, moving the data of the page into a third block; wherein a number of pages corresponding to a word line of the second block is less than a number of pages corresponding to a word line of the third block.