Flash Memory Controller Read Pattern Error Recovery
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Solution Overview
Problem
Flash memory devices face performance degradation due to high error rates and the need for extensive read retries, which increase processor overhead and slow down data recovery, especially when uncorrectable errors occur in page data.
Innovation Solution
A flash memory device configuration that includes a processor and a flash memory controller, which holds a read pattern specifying the order of selection for read options and executes error correction using these options to retry reads, reducing processor intervention and expediting data recovery by merging user data from multiple reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor receives the result of a read retry and issues an instruction to retry the read with a different read parameter, then the possibility to read data successfully is increased, but large overhead on the processor occurs and long time is required for the read retries
Solution Approach 1:
The flash memory controller autonomously manages read retries by automatically selecting different read parameters from a predefined read pattern when error correction fails, without requiring processor intervention. The controller designates the next read option based on the read pattern and executes subsequent reads independently, allowing the system to serve itself during error recovery operations.
Solution Approach 2:
The read pattern is pre-configured with multiple read options (different read parameters) before read operations begin. When a read fails initial error correction, the controller can immediately proceed to the next predefined read option in the pattern, eliminating the need for real-time parameter selection and reducing retry time.
2Reliability
If the processor receives the result of a read retry and further issues an instruction to retry the read with a different read parameter, then data recovery possibility is improved, but the processor overhead increases
Solution Approach 1:
The flash memory controller independently handles the entire read retry process, including error correction attempts and subsequent reads with different parameters. The controller designates next read options and executes retries without processor involvement, transferring the recovery burden from the processor to the controller itself and reducing processor overhead.
Solution Approach 2:
The read retry functionality is segmented into distinct components: the processor handles initial read commands, while the flash memory controller autonomously manages error correction and retry operations. This segmentation allows the processor to focus on high-level operations while the controller handles detailed error recovery tasks.
3Reliability
If data retrieved from a given page includes an uncorrectable error, then the page data is uncorrectable and data recovery is needed, but it takes more time for a RAID function to recover the data using data in other flash memory devices
Solution Approach 1:
The system performs error correction using multiple read options from the read pattern before resorting to RAID recovery. By pre-configuring read patterns with various parameters and attempting correction locally first, the system avoids the time-consuming RAID recovery process in many cases, preserving high-speed performance while maintaining reliability.
Solution Approach 2:
The read pattern provides a cushion of multiple predefined read options that can be attempted before data recovery becomes necessary. This beforehand preparation with multiple read parameters creates a buffer that may resolve errors without requiring external RAID intervention, thus cushioning against performance degradation.
Data Source
AI summary
A flash memory controller is configured to hold a read pattern defining an order of selection of read options specifying a parameter value for a read from the flash memory chip. The flash memory controller is configured to execute error correction on data read from the flash memory chip in accordance with the read command. The flash memory controller is configured to designate a next read option specified in the read pattern to read the data from the flash memory chip in a case where all errors in the read data are not corrected by the error correction.