Flash Memory Controller ROM Error Correction via CRC and ECC Merging
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Solution Overview
Problem
Existing semiconductor memory devices, such as NAND flash memory, face operation failures and malfunctions due to read errors in the ROM caused by power supply voltage drops or ROM defects, which are difficult to identify and correct using cyclic redundancy check (CRC) methods.
Innovation Solution
Incorporating a controller with both cyclic redundancy check (CRC) and error checking and correcting (ECC) processing units to detect and correct errors, allowing the system to transition to a safe mode and perform error correction using different algorithms for multiple operations, thereby suppressing malfunctions and facilitating failure analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If only CRC processing is used to detect ROM code errors, then the detection capability is simple and fast, but the system cannot correct errors and suffers from operation failures and malfunctions
Solution Approach 1:
The patent combines CRC processing unit and ECC processing unit into a single controller structure. The CRC unit performs initial error detection, and when errors are detected, the system transitions to safe mode where the ECC unit performs comprehensive error detection and correction. This merging approach enables both error detection and correction capabilities without requiring completely separate systems, thus improving reliability while controlling device complexity.
Solution Approach 2:
The patent implements a dynamic operational mode that transitions between normal mode and safe mode. In normal mode, the system operates with standard processing. When CRC detects errors, the system dynamically transitions to safe mode where ECC processing is activated for error correction. This dynamic adaptation allows the system to optimize between speed and reliability based on the actual error condition, resolving the contradiction between simple detection and comprehensive correction.
2Reliability
If the system operates in normal mode with CRC only, then the operation speed is fast, but error corrections are not performed leading to malfunctions
Solution Approach 1:
The patent implements a dynamic operational mode that transitions between normal mode and safe mode. In normal mode, the system operates with standard processing for fast operation. When CRC detects errors, the system dynamically transitions to safe mode where ECC processing is activated for error correction. This dynamic adaptation allows the system to optimize between speed and reliability based on the actual error condition, resolving the contradiction between simple detection and comprehensive correction.
Solution Approach 2:
The patent extracts the ECC processing function as a separate operational mode (safe mode) that is only activated when needed. Instead of always performing comprehensive ECC processing which would slow down normal operation, the system extracts this heavy processing step and only executes it when CRC error detection triggers the transition to safe mode. This selective extraction maintains fast normal operation while enabling thorough error correction when required.
3Reliability
If CRC checks are performed repeatedly without error correction, then the detection process continues, but the system cannot prevent operation failures and malfunctions
Solution Approach 1:
The patent combines CRC processing unit and ECC processing unit into a single controller structure. The CRC unit performs initial error detection, and when errors are detected, the system transitions to safe mode where the ECC unit performs comprehensive error detection and correction. This merging approach enables both error detection and correction capabilities without requiring completely separate systems, thus improving reliability while controlling device complexity.
Solution Approach 2:
The patent introduces a safe mode as an intermediary operational state between normal operation and error correction. When CRC detects errors during normal operation, the system transitions to this intermediary safe mode where ECC processing is activated. This intermediary mode acts as a bridge that allows the system to handle errors comprehensively without permanently altering the normal fast operation mode, thus managing the complexity of multiple processing algorithms while improving operational stability.
Data Source
AI summary
A semiconductor memory device and an operation method capable of suppressing malfunctions and the like and performing safe operations are provided. A flash memory of the disclosure includes a controller which controls an operation based on a code read from a ROM. The operation method of the disclosure includes detecting whether the code read from the ROM has an error by a CRC processing unit; determining whether to transition to a safe mode when the code having the error is detected; and detecting and correcting the error of the code by an ECC processing unit after transitioning to the safe mode.