Flash Memory Controller Sector Address Optimization
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Solution Overview
Problem
Conventional serial NOR flash memory addressing schemes are inefficient for performance-intensive applications due to high latency in data fetch operations, especially when accessing code stored in non-contiguous memory locations across multiple sectors.
Innovation Solution
A system and method that utilizes a memory controller with an internal table to store sector attributes, comparing current and previous sector addresses to transmit only the sector-specific memory cell address during address cycles, reducing the duration of address cycles and latency in data fetch sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complete 32-bit memory cell address is transmitted to serial flash memory during address cycle, then accurate memory cell addressing is achieved, but address cycle duration increases and latency increases
Solution Approach 1:
The 32-bit memory cell address is segmented into two parts: 8 MSBs for sector addressing and 24 LSBs for sector-specific addressing. The patent applies segmentation by transmitting only the necessary 24 LSBs when the sector address has not changed, rather than transmitting the complete 32-bit address every time. This reduces the address cycle duration while maintaining accurate memory cell addressing through the combination of stored sector address and transmitted sector-specific address.
Solution Approach 2:
The memory controller stores the sector address in an internal register during preliminary operations. When a memory cell access is required, the controller first checks whether the sector address has changed compared to the previous access. If the sector address is the same, the controller transmits only the 24 LSBs without re-transmitting the 8 MSBs that are already stored in the register. This preliminary storage of sector address enables reduced transmission time while maintaining addressing accuracy.
2Device complexity
If serial addressing is used in flash memory, then device complexity is reduced, but data fetch latency increases for non-contiguous memory locations
Solution Approach 1:
The addressing scheme is segmented into two components: sector address (8 MSBs) and sector-specific address (24 LSBs). The patent applies this segmentation by maintaining the sector address in the memory controller's internal register and only transmitting the sector-specific address when needed, thereby reducing the number of bits transmitted during address cycles while maintaining the ability to access any memory cell in the flash memory.
Solution Approach 2:
The addressing scheme becomes dynamic by adapting the transmission based on whether the sector address has changed. The memory controller dynamically determines how many address bits to transmit: full 32-bit address when sector changes, or reduced 24-bit address when sector remains the same. This dynamic approach reduces average address cycle duration while maintaining the simplicity of serial addressing architecture.
3Productivity
If execute-in-place functionality is implemented in flash memory, then productivity is improved, but access time for non-contiguous sectors increases
Solution Approach 1:
The memory controller performs preliminary action by storing the sector address in an internal register during the first access to a sector. Subsequent accesses to memory cells within the same sector can then utilize this pre-stored sector address, eliminating the need to re-transmit the 8 MSBs. This preliminary storage enables faster sequential accesses within a sector, improving execute-in-place productivity while minimizing access time penalties for non-contiguous sector transitions.
Solution Approach 2:
The address is segmented into sector address (8 MSBs) and sector-specific address (24 LSBs). The patent applies this segmentation by maintaining sector address in the controller's register and only transmitting the variable-length sector-specific address when necessary. This reduces the average number of bits transmitted during execute-in-place operations, thereby reducing access time for non-contiguous sectors while maintaining high productivity.
Data Source
AI summary
A system for operating a flash memory includes a memory controller in communication with a processor. The memory controller includes a memory read access command receiver that receives a memory read access command from the processor. The memory read access command includes a memory cell address of a memory cell to be accessed for the execution of the memory read accessed command. The memory cell address includes a current sector address and a sector specific memory cell address. The flash memory is provided with either both the current sector address and the sector specific memory cell address or only the sector specific memory cell address for generating the memory cell address.