Flash Memory Controller Data Segmentation for Write Latency
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Solution Overview
Problem
Flash memory systems face delays and errors due to the time-consuming data integration process, which exceeds the 250 ms processing limit for write commands, especially when integrating mother, FAT, and child blocks, leading to inefficiencies in data writing.
Innovation Solution
The solution involves dividing data from mother and FAT blocks into segments and writing these segments to reserved pages across multiple processing periods, allowing for efficient integration within the time constraint, thereby reducing the time required for each write operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data integration of mother block and FAT block is performed, then data writing completeness is improved, but processing time exceeds 250 ms limit
Solution Approach 1:
The patent divides the data integration process into multiple segments by creating integrated data segments from original and updated data. Instead of performing complete data integration in one operation, the system segments the data into multiple parts that can be processed separately within the 250 ms time limit, thus resolving the contradiction between data completeness and processing time.
Solution Approach 2:
The patent performs preliminary actions by preparing integrated data segments before the actual write operation. The controller pre-processes the data by integrating original data from the mother block with updated data from the FAT block, creating ready-to-write integrated data segments. This preliminary preparation enables the system to complete the write operation within the 250 ms limit while ensuring data completeness.
2Reliability
If data is written to integrated block, then data integration is achieved, but processing speed decreases
Solution Approach 1:
The patent segments both the source data (into original and updated portions) and the destination (into multiple integrated data segments). This segmentation allows the system to process and write data in smaller, faster operations rather than handling large blocks of data monolithically, thereby improving writing speed while maintaining integration accuracy.
Solution Approach 2:
The patent implements a dynamic data writing approach where the controller adaptively manages the integration and writing process. The system dynamically creates integrated data segments and writes them to the integrated block in a streamlined manner, optimizing the balance between integration accuracy and writing speed.
Data Source
AI summary
A flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks comprising a plurality of ordinary pages and a plurality of reserved pages. The controller receives a current write command and write data from a host, determines a mother block and an FAT block corresponding to the write command, divides data of the mother block and data of the FAT block into a plurality of original data segments and a plurality of updating data segments, integrates the original data segments with the updating data segments to obtain integrated data segments, writes the integrated data segments to an integrated block respectively in a plurality of processing periods of a plurality of subsequent write commands, and writes the subsequent write data to the reserved pages of a plurality of subsequent blocks.