Flash Memory Controller Data Recovery via Source Tracing
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Solution Overview
Problem
Existing data protection methods for flash memory devices, such as RAID, lead to memory space occupation and access speed degradation due to the need for parity information storage and computation, which cannot achieve a 100% data repair rate.
Innovation Solution
A data processing method using a memory controller that maintains a table to trace back data sources and perform data recovery when memory space damage occurs, allowing for 100% data repair without occupying extra memory space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RAID protection mechanism is used to protect data in flash memory device, then data reliability is improved, but memory space utilization deteriorates due to parity information storage
Solution Approach 1:
The patent extracts the data protection function from the storage medium itself and relocates it to a separate processing unit (CPU or controller). Instead of storing parity information in the flash memory device, the system calculates parity in the external processor and uses it for data recovery without occupying flash memory space. This separation resolves the contradiction by maintaining data protection while preserving full memory space utilization.
Solution Approach 2:
The patent introduces an intermediary processor (CPU or controller) that mediates between the host and flash memory device. This intermediary performs parity calculation and data recovery operations, acting as a buffer that protects data without requiring additional storage space in the flash memory device itself. The intermediary handles all computation tasks, separating the protection mechanism from the storage medium.
2Reliability
If RAID protection mechanism is used to protect data in flash memory device, then data reliability is improved, but access speed deteriorates due to parity information computation
Solution Approach 1:
The patent extracts all computation-intensive parity operations from the flash memory access path and relocates them to an external processor. This extraction eliminates the computational overhead from the memory access chain, maintaining high access speeds while preserving data protection capabilities through external parity management.
Solution Approach 2:
The intermediary processor handles all parity calculation and data recovery computations, acting as a dedicated computation unit that does not bottleneck the flash memory access path. This mediator approach allows the flash memory device to operate at full speed while the intermediary performs protection operations in parallel or during idle periods.
3Reliability
If parity information is stored in flash memory device, then data recovery capability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the complexity of parity management from the flash memory device and relocates it to an external processor. This extraction simplifies the flash memory device to a pure storage medium while concentrating all protection logic and complexity in the external CPU or controller, which is better suited for handling computational complexity.
Data Source
AI summary
A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.