Flash Memory Controller Spare Area Management

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Solution Overview

Problem

The efficiency of writing sequential data in flash memory devices is hindered by the need for merging operations when remaining space in physical erasing units is insufficient, leading to reduced performance.

Innovation Solution

A data writing method that allocates logical units to physical erasing units, with spare units used to manage remaining space, issuing specific command sequences based on the availability of space to optimize data distribution and minimize merging operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sequential data is written into physical erasing units until they are full, then storage capacity is maximized, but merging operations are required when remaining space is insufficient, reducing writing efficiency

Engineering Contradiction:
Improvedata writing efficiencyVSAvoidtime for merging operations
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent introduces a spare area consisting of physical erasing units that are pre-prepared and reserved before data writing operations begin. When the data area becomes full or requires merging, the controller can immediately utilize these pre-prepared spare units to continue writing sequential data without performing time-consuming merging operations. This preliminary preparation of spare storage resources eliminates the need for frequent merging during data writing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent divides the flash memory device into distinct segments: a data area for storing sequential data and a spare area with physical erasing units reserved for handling full data area conditions. This segmentation allows the system to manage data writing and merging operations separately, enabling continuous writing to the data area while maintaining a pool of ready-to-use spare units that can be activated without disrupting the writing flow.

Inventive Principle:
Principle #1Segmentation

2Productivity

If merging operations are performed frequently to manage full physical erasing units, then storage space is recovered for continued use, but the frequency of merging operations reduces overall writing speed

Engineering Contradiction:
Improvewriting speedVSAvoidcomplexity of space management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a self-service mechanism where the spare area automatically provides physical erasing units to the data area when needed. The controller monitors the state of the data area and automatically activates spare units from the spare area without requiring complex merging operations. This self-service approach simplifies space management by allowing the system to handle full data area conditions through automatic utilization of pre-prepared spare resources, reducing both writing speed degradation and management complexity.

Inventive Principle:
Principle #25Self-service

3Quantity of substance

If all physical erasing units are used for data storage, then storage capacity is maximized, but no units remain available for handling full conditions without merging

Engineering Contradiction:
Improvestorage capacityVSAvoidwriting efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent applies partial action by allocating only a portion of the total physical erasing units to the data area while reserving another portion as a spare area. This partial utilization approach means that not all storage capacity is immediately available for data writing, but the reserved spare units provide the necessary buffer to maintain writing efficiency. The sacrifice of some immediate storage capacity in the spare area prevents the need for frequent merging operations, thereby preserving overall writing productivity.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9312011B1Data writing method, memory storage device and memory control circuit unit
Publication Date: 2016.04.12 PHISON ELECTRONICS
  • US9312011B1 patent drawing
  • US9312011B1 patent drawing
  • US9312011B1 patent drawing

AI summary

A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: writing data into at least one first logical unit and at least one second logical unit, and the data includes first data and second data; storing first data into at least one first physical erasing unit and filling the first physical erasing unit with the first data; storing second data into at least one second physical erasing unit; determining whether a remaining space of each second physical erasing unit is less than a threshold; if the remaining space of one of the at least one second physical erasing unit is less than the threshold, selecting at least one fourth physical erasing unit from a spare area and writing the second data into the at least one second physical erasing unit and the at least one fourth physical erasing unit.