Flash Memory Controller Voltage Adjustment for QLC Read Errors
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Solution Overview
Problem
Existing flash memory controllers face challenges with increased bit error rates in triple level cell (TLC) and quadruple level cell (QLC) flash memories, and data retention issues in 3D flash memory, leading to inefficient data retrieval and system performance degradation.
Innovation Solution
A flash memory controller that employs active foreground scanning to determine appropriate read voltages by analyzing the states of memory cells, adjusting voltage levels to balance cell states, and using these adjustments to improve decoding success rates and system efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sensing scheme is used for reading data from TLC flash memories, then bit error rate is reduced, but it does not work for QLC flash memories with high-level per memory cell
Solution Approach 1:
The patent implements dynamic voltage adjustment by determining the balance status of memory cell states and selectively adjusting read voltages based on this determination. The system transitions from static traditional sensing schemes to dynamic voltage adaptation, enabling the same system to effectively handle both TLC and QLC flash memories by adjusting its behavior based on detected state distribution patterns.
2Reliability
If background scanning is performed to detect quality of blocks and move valid data, then data retention issue is addressed, but system performance is degraded due to time consumption
Solution Approach 1:
The patent performs preliminary determination of memory cell state balance during normal read operations. By proactively identifying blocks with unbalanced states that indicate data retention issues, the system can take preliminary corrective actions (adjusting read voltages) before data becomes completely unreadable, thereby addressing data retention problems without requiring extensive background scanning operations that would degrade system performance.
Solution Approach 2:
The system uses the readout information from normal read operations to self-diagnose the health status of memory blocks by analyzing the balance of memory cell states. This self-service mechanism allows the flash memory controller to detect and respond to data retention issues using existing read operations, eliminating the need for separate, time-consuming background scanning processes.
3Productivity
If flash memory controller is always busy with data operations, then productivity is maintained, but there is not enough time to perform background scanning
Solution Approach 1:
The patent merges the data read operation with the health monitoring function by analyzing the balance of memory cell states during normal read operations. This combination allows the system to perform both data retrieval and retention monitoring simultaneously, eliminating the need for separate background scanning operations and ensuring that reliability monitoring does not compromise productivity.
Data Source
AI summary
The present invention provides a method for access a flash memory module, wherein the method includes the steps of: sending a read command to the flash memory module to read a plurality of memory cells of at least one word line of the flash memory module by using a plurality of read voltages, wherein each memory cell is configured to store a plurality of bits, each memory cell has a plurality of states, the states are used to indicate different combinations of the plurality of bits; obtaining readout information from the flash memory module; analyzing the readout information to determine numbers of the states of the memory cells; determining if the memory cells are balance or unbalance according the numbers of the states of the memory cells to generate a determination result; and referring to the determination result to adjust voltage levels of the plurality of read voltages.