Flash Memory Block-Page Reading Conversion Coefficient
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Solution Overview
Problem
Current methods for determining the conversion relationship between block reading and page reading in flash memory chips are inaccurate, leading to inefficient data migration and increased bit error rates, as they assume equal weights for both operations, which is not reflective of actual usage patterns in SSDs where page reading is more common.
Innovation Solution
A method and system that involves writing random numbers to a test sample block, performing multiple iterations of block and page reading, recording bit error rates, and calculating a conversion coefficient to accurately determine the number of page reads equivalent to block reads, thereby setting a threshold for data migration and reducing error recovery processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the weights of block reading and page reading are deemed to be the same (simple conversion method), then the conversion process is simple, but the accuracy of the conversion result is low
Solution Approach 1:
The patent changes the parameter of reading operation types from a uniform weight assumption to differentiated weight values. By introducing different weight coefficients for block reading (first weight value) and page reading (second weight value), the system accurately reflects the actual impact of different reading operations on reading interference, thereby resolving the contradiction between simple conversion and accurate conversion results
Solution Approach 2:
The patent implements dynamic weight adjustment based on flash memory chip characteristics and actual usage patterns. The weight values for block reading and page reading are not fixed but are determined through testing and analysis of the specific chip's behavior, allowing the conversion relationship to adapt to different chip types and usage scenarios, thus improving accuracy while maintaining reasonable complexity
2Reliability
If data migration is performed based on inaccurate conversion, then the migration threshold may be reached prematurely or delayed, but the reading interference and bit error rate increase
Solution Approach 1:
The patent establishes a feedback mechanism where the conversion relationship is continuously optimized based on actual bit error rate data and reading interference observations. By monitoring the actual performance and adjusting the weight values accordingly, the system ensures that data migration is triggered at the optimal moment, preventing both premature migration (which reduces productivity) and delayed migration (which compromises reliability)
Solution Approach 2:
The patent performs preliminary testing and analysis to determine the conversion relationship before actual usage. By conducting pre-characterization tests on flash memory chips to establish the weight values for different reading operations, the system prepares accurate conversion parameters in advance, enabling optimal migration decisions during actual operation and avoiding the need for real-time adjustments that would reduce efficiency
Data Source
AI summary
A method and device for testing a conversion relationship between different reading manners in a flash memory chip and a readable storage medium are provided. Block reading is respectively performed, a bit error rate file is recorded, a test starting point, a test ending point and a test step length are is set in a block, the bit error rate file of the number of times of corresponding page reading is respectively recorded, and the number of times of page reading that is closest to the proportion of block error codes are found from the proportion of page error codes, a conversion of the number of times of block reading and the number of times of page reading is completed, conversion coefficients of the block reading and the page reading can be calculated for blocks in different states of a life cycle.