Flash Memory Serial-to-Parallel Converter Area Reduction
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Solution Overview
Problem
Existing flash memories face limitations in data communication speed and efficiency due to the use of serial input/output methods, which result in significant area consumption and reduced programming efficiency.
Innovation Solution
The implementation of a flash memory system that converts serial data into parallel data and applies inversion processing using a serial-to-parallel converter and a data mode decision circuit, including a digital-to-analog converter, level shifter, and inversion circuit, to improve data communication speed and reduce programming currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If serial input/output method is used, then area consumption is reduced, but data communication speed becomes limited
Solution Approach 1:
The patent transitions from serial (one-dimensional) data input to parallel (multi-dimensional) data input by introducing a serial-to-parallel converter. This converter receives serial data and converts it into parallel data, enabling multiple data bits to be processed simultaneously, thereby significantly improving data communication speed while maintaining a compact device structure.
2Area of stationary object
If serial input/output method is used, then device size is reduced, but programming efficiency becomes low
Solution Approach 1:
The patent employs parallel data processing architecture that converts serial input into parallel processing paths. The serial-to-parallel converter enables multiple data lines to operate simultaneously, dramatically improving programming efficiency without increasing device size, as the parallel processing occurs within the existing device footprint.
3Use of energy by moving object
If bit inversion technique is adopted to reduce current loading, then area consumption increases due to inversion control signals
Solution Approach 1:
The patent applies inversion processing to data before it is written into the flash memory chip. The data mode decision circuit determines which data requires inversion and performs the inversion in advance, generating inversion control signals that guide the parallel data writing process. This preliminary inversion action reduces the current loading on the charge pump during programming while minimizing the area consumed by control signal infrastructure.
Data Source
AI summary
A flash memory is disclosed. The flash memory includes a flash memory chip; a serial-to-parallel converter for receiving and converting a serial data to a parallel data; and a data mode decision circuit connected to an output terminal of the serial-to-parallel converter for generating an inversion control signal through the parallel data and for applying an inversion processing to the parallel data and then outputting an inverted parallel data to the flash memory chip under the control of the inversion control signal. By converting the serial data to a parallel data and then writing the parallel data into the flash memory chip, a lower proportion of the inversion control signal to the total amount of data is achieved, and therefore less area is consumed while the same programming efficiency and average programming power is maintained compared with a flash memory adopting the bit inversion technique of the prior art.