Multi-Layer Flash Memory Programming Mode for Floating Gate Coupling
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Solution Overview
Problem
Multi-layer storage flash memory devices experience a severe floating gate coupling effect, leading to lower reliability and higher error rates compared to single-layer devices, which interferes with data integrity and reduces the service life of flash memory controllers.
Innovation Solution
Implementing three specific programming modes that skip certain logic pages during the programming process to mitigate the floating gate coupling effect, including skipping LSB pages in horizontal, diagonal, and vertical directions, and a switching control method to adapt programming modes based on error thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-layer storage flash memory performs multiple programming operations to save multi-bit data, then storage capacity is increased, but the floating gate coupling effect intensifies and reliability decreases
Solution Approach 1:
The patent segments the programming process into multiple passes, where each pass programs a specific subset of pages. By dividing the programming operation into sequential passes that target different page groups, the system reduces the cumulative floating gate coupling effect while still achieving multi-bit data storage through repeated operations.
Solution Approach 2:
The patent implements preliminary actions by skipping certain page groups in early programming passes. Specifically, LSB pages are skipped in the first pass and MSB pages are skipped in the second pass, performing preliminary selective programming to minimize floating gate coupling before completing the full multi-bit storage operation.
2Productivity
If programming operations are performed on all logic pages sequentially, then complete data programming is achieved, but floating gate coupling effect increases and error rate increases
Solution Approach 1:
The patent performs preliminary selective programming by skipping specific page groups in the first pass (LSB pages) and second pass (MSB pages). This preliminary action reduces the total number of sequential programming operations that cause floating gate coupling, thereby lowering the error rate while still achieving complete data programming through the multi-pass process.
Solution Approach 2:
The patent applies the skipping principle by deliberately omitting certain page groups from programming operations in specific passes. LSB pages are skipped in the first pass and MSB pages are skipped in the second pass, rushing through the programming process by avoiding redundant operations that would increase floating gate coupling and errors.
3Reliability
If multiple programming passes are performed to program all pages, then complete programming is achieved, but time consumption increases
Solution Approach 1:
The patent performs preliminary selective programming in the first and second passes, skipping certain page groups to reduce the number of operations needed. By completing the essential programming tasks in these preliminary passes before performing the full sequential programming, the system reduces overall time consumption while maintaining programming completeness.
Solution Approach 2:
The patent applies skipping to reduce programming time by omitting redundant operations. LSB pages are skipped in the first pass and MSB pages are skipped in the second pass, allowing the system to rush through the programming process by avoiding unnecessary sequential operations while still achieving complete programming through the multi-pass structure.
Data Source
AI summary
The present invention relates to a programming mode for improving the reliability of a multi-layer storage flash memory device in a semiconductor storage field. The present invention provides several programming modes for improving the reliability of a multi-layer storage flash memory device and switching control methods thereof, based on the technical conception of skipping some specific logic pages in the programming process to reduce the impact of the floating gate coupling effect on the operation of the flash memory. By skipping some logic pages, the present invention effectively reduces the floating gate coupling effect in the horizontal, diagonal and vertical directions of the multi-layer storage flash memory in the programming process. Therefore, the error rate is reduced, the service life of the device is prolonged, and the reliability of the whole system is enhanced.