Flash Memory Error Checking with CRC and ECC Segmentation
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Solution Overview
Problem
Conventional flash memory systems experience inefficiencies in data access time due to the need to read and correct entire memory segments, even when only accessing 512-byte data, which prolongs error detection and correction processes.
Innovation Solution
An electronic storage device with a controller that generates both Cyclical Redundancy Check (CRC) and Error Check and Correction (ECC) codes, allowing for efficient error detection and correction by checking CRC codes for 512-byte data and ECC codes for 1024-byte data, thereby reducing the need to read entire memory segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire memory segment is read for error detection and correction, then error detection and correction capability is ensured, but data access time is prolonged
Solution Approach 1:
The patent segments the error detection and correction process into two distinct stages: first using CRC codes for quick error detection on the requested data portion, and only if errors are detected, then using ECC codes for comprehensive error correction. This segmentation allows the system to avoid the time-consuming full ECC processing when no errors are present, thus resolving the contradiction between reliability and access time.
Solution Approach 2:
The patent applies partial action by using only the necessary error correction mechanism for each case. For error-free data, only lightweight CRC checking is performed. For erroneous data, the full ECC correction is applied. This partial application of error correction measures optimizes the balance between reliability and access time by avoiding excessive processing when not needed.
2Loss of time
If CRC code is used for error detection, then data access time is shortened, but error detection capability for larger data sizes is reduced
Solution Approach 1:
The patent segments error detection into two layers: CRC for initial quick detection and ECC for comprehensive correction when needed. This segmentation allows CRC to handle the time-sensitive aspect while ECC provides the robust reliability guarantee, effectively resolving the contradiction between speed and capability.
Solution Approach 2:
The patent introduces CRC as an intermediary mechanism between the data and the full ECC system. CRC acts as a fast filter that handles most cases, while ECC serves as the backup for actual error correction. This intermediary approach allows the system to achieve both fast access times and robust error detection capability.
Data Source
AI summary
An electronic storage device for connecting with a host system includes a flash memory including a number of memory segments, and a controller including an error correction segment capable of generating a first correction code and a second correction code according to a written data received by the controller. The written data, the first correction code and the second correction code are written into a memory segment of the flash memory by the controller. The first correction code is used for checking whether there is an error bit in the written data, and the second correction code is used for checking and correcting said error bit in the written data.