Flash Memory CSL Feedback Circuit for Noise Reduction
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Solution Overview
Problem
Flash memory devices face challenges in maintaining narrow threshold voltage distributions due to common source line (CSL) noise, which affects data retention and programming accuracy in multi-level cell (MLC) devices.
Innovation Solution
The implementation of a CSL feedback circuit and CSL feedback control logic that detects voltage changes in the common source line and compensates the selected word or bit line to maintain a constant voltage level during sensing operations, independent of CSL voltage changes, thereby preventing the spreading of threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory devices use multi-level cells (MLC) to increase storage capacity, then data storage capacity is improved, but threshold voltage distributions spread out due to CSL noise causing programming accuracy to deteriorate
Solution Approach 1:
The patent implements a common source line (CSL) feedback circuit that detects voltage changes on the CSL and applies compensating voltages to word lines or bit lines. This feedback mechanism counteracts CSL noise effects, maintaining narrow threshold voltage distributions and improving programming accuracy while preserving the high storage capacity of MLC devices
Solution Approach 2:
The patent dynamically adjusts voltage parameters (word line voltages or bit line voltages) based on detected CSL voltage changes. By changing these voltage parameters in real-time compensation, the system maintains adequate margins between threshold voltage distributions despite the presence of CSL noise, thereby improving programming accuracy
2Productivity
If flash memory devices perform read operations on MLCs, then data retrieval is enabled, but CSL noise causes threshold voltage distributions to spread reducing data retention reliability
Solution Approach 1:
The CSL feedback circuit operates during read operations to detect and compensate for voltage changes on the common source line. This real-time feedback compensation prevents threshold voltage distribution spreading, maintaining reliable data retention while enabling fast data retrieval from MLC devices
Solution Approach 2:
The feedback circuit applies compensating voltages before CSL noise can significantly affect the read operation. By counteracting the noise effects in advance, the system prevents threshold voltage spreading and maintains data retention reliability throughout the read operation
3Productivity
If flash memory devices increase programming speed, then productivity is improved, but CSL noise effects become more significant causing threshold voltage distributions to spread
Solution Approach 1:
The feedback circuit provides real-time compensation during high-speed programming operations, detecting CSL voltage changes and applying corrective voltages to maintain narrow threshold voltage distributions. This enables fast programming while preserving programming precision
Solution Approach 2:
The feedback compensation operates continuously throughout the programming process, ensuring that threshold voltage distributions remain narrow even during high-speed operations. This continuous compensation maintains manufacturing precision without sacrificing programming speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces noise-induced errors, maintaining accurate data storage and programming by keeping the threshold voltage distributions narrow, enhancing the reliability of flash memory devices.
Implementation Method 1
a CSL feedback circuit connected to the common source line to detect a voltage level of the common source line
Implementation Method 2
CSL feedback control logic configured to control a voltage level of a selected word line or a selected bit line to be compensated to a constant level based on the voltage level detected by the CSL feedback circuit
Data Source
AI summary
A flash memory device comprises memory cells connected between a bit line and a common source line, word lines connected to the memory cells, a common source line feedback circuit connected to a common source line (CSL) to detect the voltage level of the common source line, and a CSL feedback control logic configured to control a voltage level of a selected word line or a selected bit line to be compensated to a substantially constant value during a sensing operation of the memory cells based on the detected voltage level of the CSL.


