Flash Memory Data Band Allocation for Error Distribution

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Solution Overview

Problem

Conventional RAID systems are inefficient in managing error distribution in solid-state memory devices like NAND flash, where error rates vary significantly across different pages due to quantum phenomena such as charge migration, leading to inefficiencies in error correction and reduced storage capacity.

Innovation Solution

A distribution controller is used to allocate data bands across a memory array with unevenly distributed error rates, ensuring each data band has a collective error rate within a preselected range by selectively distributing data across storage channels with varying reliability, employing an asymmetric or diagonal writing pattern to balance error likelihood.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is stored in flash memory devices with sequential page writing, then storage capacity is increased, but error rate becomes unevenly distributed across pages

Engineering Contradiction:
Improvestorage capacityVSAvoiderror rate distribution
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies local quality by treating different pages of flash memory with different error correction strategies. Specifically, pages are divided into groups where early pages (with lower error rates) receive less ECC overhead while later pages (with higher error rates due to charge accumulation) receive more robust ECC protection. This localized differentiation optimizes the balance between storage capacity and reliability by matching protection levels to actual error characteristics of each page region.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of error correction code strength based on page position. By dynamically adjusting ECC parameters (such as code rate or redundancy level) according to the page's position in the sequence, the system adapts to the varying error rates caused by charge migration. Early pages use parameters optimized for low error rates, while later pages use parameters designed for higher error rates, thereby maintaining overall system reliability without excessive overhead.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If conventional RAID writes data promiscuously to all disks concurrently, then storage speed is improved, but error distribution becomes unbalanced in solid state disks

Engineering Contradiction:
Improvestorage speedVSAvoiderror distribution
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the data writing process into distinct phases or groups corresponding to different page ranges across multiple flash devices. Instead of writing to all pages concurrently across all devices, the system divides pages into segments (e.g., early pages group, later pages group) and manages error correction independently for each segment. This segmentation allows balanced error distribution while maintaining parallel writing performance within each segment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces asymmetry in the writing pattern across flash devices, deliberately offsetting which pages are written to which devices rather than using a symmetric round-robin approach. This asymmetric distribution ensures that pages with similar error characteristics (e.g., all high-error-rate pages) are not concentrated on the same device or in the same data band, thereby balancing the error distribution across the RAID array while preserving parallel write performance.

Inventive Principle:
Principle #4Asymmetry

3Reliability

If error correction overhead is increased to handle high error rates, then data reliability is improved, but storage efficiency decreases

Engineering Contradiction:
Improvedata integrityVSAvoidstorage efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by implementing variable error correction overhead across different page groups rather than using a uniform overhead for all pages. Pages are categorized into groups with different error rate characteristics, and each group receives error correction codes tailored to its specific error profile. This results in lower ECC overhead for low-error pages and higher overhead only where necessary for high-error pages, optimizing the trade-off between reliability and storage efficiency.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies partial error correction action by providing differential protection levels rather than uniform excessive protection. Instead of applying maximum error correction overhead to all pages, the system applies partial correction (lower overhead) to pages that don't require it and reserves excessive correction (higher overhead) only for pages that actually need it due to high error rates. This partial differentiation improves storage efficiency while maintaining adequate reliability.

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively manages error distribution, enhancing data integrity and reducing the need for excessive error correction overhead, thereby improving storage efficiency and reliability in solid-state memory arrays.

Implementation Method 1

One major cause of errors in such flash memory devices are quantum phenomena, such as charge migration.

Methodology Applied
Scientific EffectCharge migration:

Data Source

PatentUS9448883B1System and method for allocating data in memory array having regions of varying storage reliability
Publication Date: 2016.09.20 CADENCE DESIGN SYST INC
  • US9448883B1 patent drawing
  • US9448883B1 patent drawing
  • US9448883B1 patent drawing

AI summary

A system and method are provided for efficient allocation of data in a memory array having regions of varying storage reliability. Storage locations for bands of data are selectively allocated in a manner which evenly distributes the probability of error in the data when stored in the memory array in spite of the varying storage reliability. A distribution controller is provided to effect such distribution of data to maintain a collective error rate of each data band within a preselected or predetermined range. The system and method also generally provide for storing at least a first and a second data band in different corresponding sets of storage channels. The system and method also generally provide for at least one of the data bands being stored in regions of differing reliability across the set of storage channels therefor.