Flash Memory Data Management via Multi-Chip Block Merging
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Solution Overview
Problem
Flash memory updating processes are inefficient due to limitations in overwriting and erasing data, leading to performance issues during the merging of blocks, which affects the overall performance of the flash memory apparatus.
Innovation Solution
A data managing method for flash memory that involves writing new data to a second block on a different flash chip and merging it with the original block, allowing for simultaneous access and real-erasing of the original block, utilizing a controller to manage the process across multiple flash chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is updated in flash memory by writing to a new block and merging with the original block, then updating performance is improved, but the complexity of data management increases due to the need to manage multiple blocks and translation tables
Solution Approach 1:
The flash memory is divided into multiple physical blocks that can be independently managed. The translation table is segmented to map logical block addresses to physical block addresses across multiple flash chips. This segmentation allows parallel operations on different blocks while maintaining a unified logical view, improving updating performance without overwhelming complexity.
Solution Approach 2:
A translation table acts as an intermediary between logical block addresses and physical block addresses. This intermediary structure simplifies data management by abstracting the physical layout details from the logical structure, allowing the system to manage multiple blocks and flash chips through a unified address space without direct complexity.
2Quantity of substance
If the flash memory apparatus performs real-erasing of a block to free up space, then storage capacity is improved, but access performance deteriorates because the apparatus cannot be written to or read from during the erasing process
Solution Approach 1:
The flash memory system is segmented into multiple independent flash chips and blocks. When one block is being real-erased, other blocks remain accessible. This segmentation enables concurrent operations where erasing occurs in isolation while other data operations continue on different blocks, maintaining overall access performance.
Solution Approach 2:
Before real-erasing a block, the system first copies all valid data from the block to be erased into a new block. This preliminary action completes the data migration before the actual erasing begins, ensuring that the erasing process does not interrupt ongoing read or write operations on other data.
3Reliability
If flash memory uses a block as the minimum unit for erasing, then reliability is improved, but updating efficiency deteriorates because data must be copied to a new block and then merged, increasing the time required for updates
Solution Approach 1:
Multiple update operations are merged into a single background merging process. Instead of immediately erasing each modified block separately, the system batches multiple block merges into one operation that occurs in the background, reducing the total time spent on updates while maintaining reliability through proper sequencing.
Solution Approach 2:
The merging process is performed periodically in the background rather than immediately after each update. This periodic action allows update operations to complete quickly without blocking, while the merging and erasing operations are scheduled during idle periods, reducing overall update time without compromising data reliability.
Data Source
AI summary
A data management method for a flash memory apparatus, entailing a step for handling a plurality of flash chips, a step for enabling the flash chips in sequence, and a step for updating the first data in the first block on the first flash chip among the flash chips. Additionally there is a step for updating f writing of the first new data corresponding to the first data into a second block in a second flash chip among the flash chips, and a step merging the first block and the second block, wherein both of the first new data and the first data are corresponding to a first logical block address.