Flash Memory Data Stripes for Parallel Write Performance
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Solution Overview
Problem
Flash memory devices face limitations in lifespan due to finite programming and erasing cycles, and experience slow writing performance as data is typically written at the block level, requiring all pages in a block to be erased before writing can commence.
Innovation Solution
The implementation of data stripes in flash memory devices, where data is segmented and written to multiple blocks concurrently, optimizing the number of blocks and pages to enhance writing performance and reduce program and erase cycles, thereby extending device lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written to flash memory at the block level with all pages erased before writing, then writing completeness is ensured, but writing time increases significantly
Solution Approach 1:
The patent segments the flash memory into multiple independent stripes, each consisting of multiple blocks. Instead of erasing and writing to one large block at a time, the system divides data into smaller segments that can be written to multiple stripes concurrently. This segmentation allows parallel processing of write operations across different blocks, reducing overall writing time while maintaining data integrity through the stripe structure.
2Reliability
If multiple program and erase cycles are performed to ensure data storage, then data reliability is improved, but device lifespan decreases due to finite transistor endurance
Solution Approach 1:
The patent implements preliminary erasure of entire stripes (groups of blocks) before writing new data, rather than erasing individual blocks when updates are needed. This preliminary action prepares the storage structure in advance, allowing multiple write operations to proceed without repeated erasure cycles. By erasing at the stripe level rather than block level, the system reduces the total number of program-erase cycles, thereby extending device lifespan while maintaining data reliability.
3Device complexity
If data is written sequentially to single blocks, then device complexity is minimized, but writing performance deteriorates due to inability to parallelize operations
Solution Approach 1:
The patent introduces a new dimensional organization by creating stripes that span multiple blocks across different dimensions of the flash memory architecture. Instead of linear sequential writing within single blocks, data is distributed across multiple blocks in a stripe structure, enabling parallel write operations. This dimensional change from single-block sequential access to multi-block parallel access significantly improves writing performance while maintaining manageable complexity through structured addressing.
Data Source
AI summary
Data stripes and addressing for flash memory devices are provided. Flash memory devices illustratively have a plurality of programmable devices that are capable of simultaneously storing data. A plurality of erasure blocks are within each of the programmable devices, and each erasure block has pages of transistors. The flash memory devices are logically organized as a plurality of stripes. Each stripe has a height and a width. In an embodiment, the stripe height is greater than one page. In another embodiment, the stripe width is less than all of the programmable devices within the flash memory device.