Flash Memory Device DDD Ion Implant Leakage Reduction

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Solution Overview

Problem

In stacked gate type flash EEPROM devices, the reduction of gate length below the sub-micron level leads to increased leakage current between the source and drain junctions, degrading the program characteristic, and increasing the cell threshold voltage ion implant dosage to compensate for this issue lowers the cell current without significant advantages.

Innovation Solution

Implementing a Double Doped Drain (DDD) ion implant process that targets both the source and drain junctions of the cell transistor, narrowing the depletion width and enhancing the pinch-off phenomenon in the gate to drain overlap region, thereby reducing leakage current and improving the program characteristic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the gate length is reduced below the sub-micron level to improve device scaling, then device density is improved, but leakage current increases between source and drain junctions

Engineering Contradiction:
Improvedevice densityVSAvoidleakage current
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies different doping concentrations locally within the drain region. The DDD ion implant process creates a first drain region with a first doping concentration and a second drain region with a second doping concentration that is higher than the first. This local variation in doping quality allows the device to maintain small gate length for high density while controlling leakage current through the localized high-doping region.

Inventive Principle:
Principle #3Local quality

2Reliability

If the cell threshold voltage ion implant dosage is increased to compensate for leakage current, then program characteristic is improved, but cell current is lowered

Engineering Contradiction:
Improveprogram characteristicVSAvoidcell current
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent changes the doping concentration parameter within the drain region to control device characteristics. By implanting DDD ions at a higher doping concentration in the second drain region compared to the first drain region, the patent achieves improved program characteristic through enhanced hot carrier generation while maintaining adequate cell current, avoiding the need to increase cell threshold voltage ion implant dosage.

Inventive Principle:
Principle #35Parameter changes

3Object-generated harmful factors

If the DDD ion implant process is applied to both source and drain junctions to narrow depletion width and enhance pinch-off, then leakage current is reduced and program characteristic is improved, but the number of ion implant processes increases

Engineering Contradiction:
Improveleakage currentVSAvoidnumber of ion implant processes
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent combines the DDD ion implant process to simultaneously treat both source and drain junctions. By applying the same ion implantation technique to both junctions, the patent achieves coordinated depletion region control and pinch-off enhancement at both interfaces, reducing leakage current effectively while using a unified process approach rather than separate treatments.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The DDD ion implant process effectively reduces leakage current and enhances the program characteristic by facilitating rapid pinch-off and increasing hot carrier generation, allowing for improved electric field strength without the need for increased cell threshold voltage ion implant processes.

Implementation Method 1

Implementing a Double Doped Drain (DDD) ion implant process that targets both the source and drain junctions of the cell transistor

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

The strong electric field so generated accordingly generates hot carriers, and electrons of the hot carriers accumulate on the floating gate

Methodology Applied
Scientific EffectHot carrier generation: Electron Avalanche

Data Source

PatentUS7429512B2Method for fabricating flash memory device
Publication Date: 2008.09.30 HUSKY INJECTION MOLDING SYST LTD
  • US7429512B2 patent drawing
  • US7429512B2 patent drawing
  • US7429512B2 patent drawing

AI summary

A method of fabricating a flash memory device. A DDD ion is implanted into a high voltage PMOS transistor and into source and drain junctions of a cell transistor in order to facilitate a pinch-off phenomenon in the gate to drain overlap region and also increase the number of hot carriers. Accordingly, a program characteristic can be improved, a depletion width between source and drain junctions of a cell can be narrowed and the leakage current can be reduced.