Flash Memory Debug Circuit Automatic Error Reporting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flash memory controllers rely solely on internal processing for generating and checking debug information, leading to unreliable test results, as they do not involve external flash memory devices in the debug information generation and handling process.
Innovation Solution
A flash memory device coupled to a flash memory controller through a specific communication interface, featuring an I/O control circuit, command and address registers, a memory cell array, address decoders, a status register, and a control circuit with a debug circuit that generates and transmits debug information without causing errors in the memory cell array, allowing for simulated or true failure scenarios to be tested.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the flash memory controller processes debug information internally only, then the device complexity is reduced, but the reliability of test results deteriorates
Solution Approach 1:
The patent divides the debug information processing function into two segments: the flash memory device generates debug information locally through its control circuit, and the flash memory controller receives and processes this information. This segmentation allows the device to provide reliable test results while maintaining manageable complexity by distributing functions across components.
Solution Approach 2:
The patent introduces an intermediary communication interface between the flash memory device and controller. This intermediary mechanism enables the device to transmit debug information to the controller without requiring the controller to directly manage all debug operations, thereby improving reliability while keeping the controller's complexity manageable.
2Measurement precision
If the debug circuit controls the memory cell array to generate actual failures, then the measurement precision of error handling is improved, but the harmful factors increase due to potential data corruption
Solution Approach 1:
The patent creates a copy of the failure scenario by generating debug information that represents potential errors without actually corrupting the memory cell array data. The control circuit produces debug information indicating simulated failures, allowing precise measurement of error handling capabilities while avoiding the harmful effects of actual data corruption.
Solution Approach 2:
The patent performs preliminary error detection by generating debug information before actual failures occur. The control circuit identifies potential failure conditions in advance and reports them through debug information, allowing the system to measure error handling precision without letting actual harmful failures propagate.
Data Source
AI summary
A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends a debug injection set-feature signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of an access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, without controlling a memory cell array of flash memory device generating errors.