Flash Memory Debug Circuit for Error Injection and Verification

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional flash memory controllers rely solely on internal processing for generating and checking debug information, leading to unreliable test results, as they do not involve external flash memory devices in the process, which can result in inaccurate error handling during debug operations.

Innovation Solution

A flash memory device coupled to a flash memory controller through a specific communication interface, featuring an I/O control circuit, command and address registers, a memory cell array, address decoders, a status register, and a control circuit with a debug circuit that generates and transmits debug information without causing errors in the memory cell array, allowing for simulated or true failure scenarios to be tested externally.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the flash memory controller processes debug information internally only, then the device complexity is reduced, but the reliability of error handling deteriorates

Engineering Contradiction:

Improvereliability of error handlingVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The system is divided into two independent but cooperative parts: the flash memory controller that generates debug information and the flash memory device that stores and returns it. This segmentation allows each component to focus on specific functions, improving overall reliability without significantly increasing complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The flash memory device acts as an intermediary that receives debug information from the controller, stores it in its memory cell array, and returns it during read operations. This intermediary mechanism enables external verification of error handling while maintaining a relatively simple controller design.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If the flash memory device is involved in generating and checking debug information, then the measurement precision of test results is improved, but the device complexity increases

Engineering Contradiction:

Improveaccuracy of test resultsVSAvoiddevice complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The flash memory device is designed to perform multiple functions: normal data storage and the additional function of storing and returning debug information. By making the device universal, the system achieves more accurate testing without adding separate dedicated hardware components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The flash memory device serves itself by using its own memory cell array to store debug information and its own read operations to return the information to the controller. This self-service approach improves measurement precision while avoiding the need for external testing equipment.

Inventive Principle:

Principle #25Self-service

3Adaptability or versatility

If the debug circuit controls the memory cell array to generate errors, then the comprehensive debugging capability is improved, but the reliability of normal operation deteriorates

Engineering Contradiction:

Improvecomprehensive debugging capabilityVSAvoidreliability of normal operation

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The system dynamically switches between normal operation mode and debug mode. During normal operation, the memory cell array functions reliably for data storage. During debug operations, the debug circuit can control error generation in the memory cell array to test error handling capabilities. This dynamic switching allows comprehensive debugging while maintaining normal operational reliability.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

Error generation in the memory cell array is performed periodically during specific debug operations rather than continuously. The debug circuit generates errors only when triggered by debug commands, allowing comprehensive testing of error handling while ensuring normal operation reliability during non-debug periods.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS12112816B2Flash memory scheme capable of controlling flash memory device automatically generating debug information and transmitting debug information back to flash memory controller with making memory cell array generating errors

Publication Date: 2024.10.08 SILICON MOTION INC

AI summary

A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends an error injection access command signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of the error injection access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, with controlling a memory cell array of flash memory device generating failure errors.