Flash Memory Debug Circuit for Automatic Error-Free Test Data Transmission
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Solution Overview
Problem
Conventional flash memory controllers rely solely on internal processing for generating and checking debug information, leading to unreliable test results, as they do not involve external flash memory devices in the process, resulting in potential errors during program, cache program, or erase operations.
Innovation Solution
A flash memory device coupled to a flash memory controller through a specific communication interface, featuring an I/O control circuit, command and address registers, a memory cell array, address decoders, a status register, and a control circuit with a debug circuit that generates and transmits debug information without causing errors in the memory cell array, allowing for simulated or true failure scenarios to be tested externally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the flash memory controller processes debug information internally without involving the flash memory device, then the control process is simple, but the test result reliability deteriorates
Solution Approach 1:
The flash memory device serves as an intermediary component in the debug information processing chain. The control circuit generates debug information and transmits it to the flash memory device, which then transmits it back to the controller. This intermediary involvement ensures that the flash memory device's actual performance is tested, improving reliability while maintaining manageable system complexity through standardized communication interfaces.
2Reliability
If the debug circuit controls the voltage generator to make the memory cell array generate errors, then true failure scenarios can be tested, but the memory cell array performance is affected
Solution Approach 1:
The system segments the memory array into multiple planes, with at least one plane designated as a test plane distinct from the main storage plane. The control circuit can selectively generate debug information for specific planes without affecting the entire memory cell array. This segmentation allows true failure scenario testing while isolating the impact to specific test areas, preserving the performance of the main storage array.
Data Source
AI summary
A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends a debug injection command signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of the debug injection command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, without controlling a memory cell array of flash memory device generating errors.